Keyssa Systems, Inc.

Kawasaki Lsi U.s.a., Inc.

Kawasaki Microelectronics America Inc.

Jerome Jean Ribo

Bruno Tourette

Roger Dwain Isaac

Pavan Kumar Hanumolu

Benoit Roederer

A device comprises a clock data recovery (CDR) circuit. The CDR circuit has an input node to receive an input data signal, an output node, a data recovery circuit, and a self-test circuit. The CDR circuit supports a first mode of operation and a second mode of operation. In the first mode, the CDR circuit receives the input data signal at the input node and provides the input data signal to an input of the data recovery circuit, the data recovery circuit recovers first data from the input data signal, and the CDR circuit provides the first data for output at the output node. In the second mode, the self-test circuit generates a test data pattern which is provided to the output node and looped back to the input of the data recovery circuit, the data recovery circuit recovers second data from the test data pattern, and the self-test circuit checks the second data for errors.

Testing of clock and data recovery circuits

Methods, systems, and apparatus for inserting a re-timer signal between a transmitter and a receiver, including receiving, from the transmitter, an input data signal having encoded words, where each encoded word of the encoded words has a word length of a predetermined number of bits; generating, by a re-timer and based on the input data signal, a regenerated clock signal and an output data signal; determining, based on the regenerated clock signal, a timing difference between the input data signal and the output data signal of the re-timer; and applying, by the re-timer and based on the timing difference between the input data signal and the output data signal, a delay to the input data signal to generate a delayed output data signal, such that a timing difference between the input data signal and the delayed output data signal corresponds to N word lengths.

Re-timer network insertion

Systems, methods, and apparatus for generating a clock signal using re-timer circuitry, including receiving an input data signal transmitted without a reference clock signal; comparing the input data signal with a re-timer clock signal to determine a frequency difference between the input data signal and the re-timer clock signal; determining a data rate of the input data signal based on the frequency difference between the input data signal and the re-timer clock signal; and generating, based on the data rate of the input data signal, a control signal for adjusting a frequency of the re-timer clock signal to frequency-lock the re-timer clock signal with the input data signal.

Multi-data rates multi-protocol communications techniques for reference-less re-timer

Systems, methods, and apparatus for regenerating a data signal and a clock signal are provided. One of the apparatuses include clock regeneration loop circuitry configured to receive an input data signal transmitted without a reference clock signal, and to generate an output reference clock signal having an adjustable clock frequency that substantially matches a data rate of the input data signal; data detection loop circuitry configured to generate a phase offset control signal for adjusting a phase of a clock signal that samples the input data signal, and to generate, based on the phase offset control signal, a sampled input data signal; and an elastic buffer configured to generate, based on the output reference clock signal and the sampled input data signal, an output data signal that substantially aligns with the output reference clock signal, and enable the different adaptation dynamic of the loops.

Multi-protocols and multi-data rates communications

Aspects of the disclosure provide a method and an apparatus for clock and data recovery. The method and apparatus can increase jitter tolerance, and can provide recovered data with reduced jitter amplitude. The method for recovering data transmitted over a channel can include detecting a phase of a data transition within a full unit interval that includes an active zone and an inactive zone that are set based on a jitter characteristic for the channel, generating a phase directive when the phase of the data transition is located within the active zone, and adjusting a data sampling phase based on the phase directive, so that the data transmitted over the channel is sampled at a data transition edge free location.

High jitter tolerant phase comparator

When used as a test data generator, CDR internal structures may be applied to generate drift conditions in the test data. For example, a finite state machine phase shifts a clock signal, over time, driving the test data generator thereby producing a drift condition on the test data. Once the test is completed, one of the other CDRs may be used as a tester to similarly generate test data for the first CDR. CDRs may be configured in pairs for this purpose so that one may be used to test the other.

Devices and methods for testing clock and data recovery devices

A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate multi-phase oversampling technique. N phase shifted clocks are generated based on a single clock and rising edges (or falling) of the phase shifted clocks and define N sampling points where a serial data stream is sampled. The multi-phase oversampling technique provides at least two sampling points per data bit of the serial data stream at highest data rates. The sampling points divide one clock cycle of the single clock into N zones. Depending on which of the zones a data edge transition is detected, the CDR can converge the sampling points to optimal data sampling positions in the serial data stream.

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San Jose, CA, United States of America

Jerome Jean Ribo