Honeywell Information Systems Inc.

Jerome J Twibell

Jaime Calle

Earnest M Monahan

John M Woods

Knute S Crawford

Victor Michael Griswold

Robert J Johnston

Robert J Garvey

George L Parris

In a data processing unit, apparatus permits more than one central processing unit and associated control interface unit to transfer data to an input/output multiplexer. Thus, more than one central processing unit can have access to a peripheral subsystem. Apparatus is provided which causes the input/output multiplexer to receive sets of data signal groups from the control interface units in sequential order. A signal-free period null signal period is provided by the control unit interface between each set of data signal groups (e.g., each data signal group set includes a single processor sequence). The signal-free period allows the input/output multiplexer to accept waiting data signals from the next sequential control interface unit. Once begun, the transfer of the entire set of data signal groups will proceed without interruption.

Interface apparatus for data transfer through an input/output

A memory unit having a multiplicity of storage locations for the temporary storage of series of groups of data signals. When the data groups are being stored in a memory location, index signals are developed that not only identify the location of the stored signal group, but when applied to the memory unit cause the data group to be withdrawn from the memory unit. The memory unit is comprised of a first addressable multiplicity of storage locations; a second addressable multiplicity of storage locations, the contents of the second multiplicity of storage locations adapted for addressing the first multiplicity of storage locations, a counter for addressing the second multiplicity of storage locations; and control logic for controlling the counter and entry and withdrawal of data signals in the first and second multiplicity of storage locations. The second multiplicity of storage locations contain the index signals that are also the addresses of the related data signal groups in the first multiplicity of storage locations. As data signal groups are withdrawn from a first storage location in response to application of index signals, a second storage location stores the address (i.e., the index signal of the first storage location not available for storage of a data signal group). The storage of a data signal group with the concurrent development of index signals, or the withdrawal of the data signal groups can be accomplished in one clock cycle. In addition, a simultaneous storage and withdrawal of data signal groups can be accomplished in one system clock cycle.

Memory unit

An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted. The processor responds to a timer interrupt request by a special command which can only selectively clear the rollover counter to ZEROS when the interval counter is not in the process of completing another interval.

Interval timer for use in an input/output system

An automatic reconfiguration hardware capability for automatically altering the local memory/processor configuration and reinitiating a bootload sequence in the event of a failure in the start-up phase of the input/output processor bootload. The automatic reconfiguration logic is enabled when a bootload request originates from the system console or the central system. Once a bootload request is initiated, all possible local memory/input-output processor (IOPP) configurations are attempted without further manual intervention. If no configuration is successful, a bootload error indication is presented at the I0P configuration panel.

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Phoenix, AZ, United States of America

Jerome J Twibell