Dell Products Inc.

Jerome J Cartmell

Jonathan I Krasner

Ro Monserrat

Thomas Mackintosh

Michael J Scharland

James Marriot Guyer

Scott Rowlands

Julie Zhivich

Qin Wang

James Read

For each source process running on a source node, a rate of high-priority operations initiated by the first process during the period that require accessing a target node can be calculated. An average rate (e.g., an exponential moving average (EMA)) of high-priority operations initiated by the first process over a larger period of time that require accessing the target node can be calculated. Similarly, a rate of high-priority operations initiated by any process executing on a processing node during the period that require accessing the target node can be calculated, and an average rate (e.g., an EMA) of high-priority operations initiated by any such process over the larger period of time that require accessing the target node can be calculated. If one or more of the rates for the period or the average rates reach or exceed respective thresholds, corrective actions can be taken.

Traffic management on an internal fabric of a storage system

A deterministic hardware indictment process is used to indict one Compute Node (CN) of a pair of CNs in response to occurrence of a fatal error on a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) interconnecting the two CN. Status information is exchanged between the CNs on a communication medium that is separate from the NTB. The indictment process is run locally on each CN based on whatever information is available to the CN. When the CN does not receive status information from the other CN, the CN runs a self-indictment check. When status information is received, and only one CN reports an error, the indictment process indicts the compute node that reported the error. If both CNs report errors, an error severity comparison process is used to select a CN to be indicted. If the reported errors are equally severe, a default CN is indicted.

Deterministic hardware indictment in response to fatal PCIe ntb error

A storage engine has a pair of compute nodes, each compute node having a separate PCIe root complex and attached memory. The PCIe root complexes are interconnected by multiple Non-Transparent Bridge (NTB) links. The NTB resources are unequally shared, such that host IO devices are required to use a first subset of the NTB links to implement memory access operations on the memory of the peer compute node, whereas storage software memory access operations are able to be implemented on all of the NTB links. A NTB link arbitration system arbitrates usage of the first and second subsets of NTB links by the storage software, to distribute subsets of the storage software memory access operations on peer memory to the first and second subsets of NTB links, while causing all host IO device memory access operations on peer memory to be implemented on the first set of NTB links.

Non-transparent bridge selection

A storage system that includes multiple CPU hosts and PCI-E multi-host capable devices uses link selection controllers to map shared memory addresses to individual PCI-E links such that each address is accessed via only one of a plurality of PCI-E links. The addresses may be grouped into same-size segments, each of which contains only addresses mapped to the same PCI-E link. The link selection controllers monitor for state changes that affect PCI-E link availability and, in response to detection of a failure, coordinate a response that includes re-mapping the affected addresses.

System for monitoring and controlling host selection for a multi-host capable PCI-E device

A host IO devices directly implements host read operations on both local memory, and on peer memory via a PCIe non-transparent bridge. When a host read operation is received by a host IO device from a host, the host IO device uses an API to obtain the physical address of the requested data on the peer memory, and generates a PCIe Transaction Layer Packet (TLP) addressed to the address in the peer memory. The TLP addressed to an address in the peer memory is passed over the NTB to the peer compute node to retrieve the data stored in the addressed slot of peer memory. The requested data is returned to the host IO device over the NTB, stored in a buffer, and read out to the host to directy respond to the host read operation.

Growing community of inventors

Millis, MA, United States of America

Jerome J Cartmell