Nvidia Corporation

Apple Inc.

Silicon Engines, Ltd.

Electronics Products Company

Other

Nvdia Corporation

Electronic Products, Inc.

Raycer, Incorporated

Jerome Francis Duluk, Jr

James Leroy Deming

Mark Hairgrove

Cameron Buschardt

John Mashey

Brian Matthew Fahs

Lacky V Shah

Richard E Hessel

Henry Packard Moreton

Lucien Dunning

Samuel Hammond Duncan

Sushma Shrikant Trivedi

Timothy John Purcell

Jack Benkual

Jesse David Hall

Stephen L Dodgen

Patrick Richard Brown

Chenghuan Jia

Gregory Scott Palmer

Jason Rupert Redgrave

Ziyad Sami Hakura

Joseph P Bratt

Emerson S Fang

Hengwei Hsu

Eric Brian Lum

Vaughn Todd Arnold

Gentaro Hirota

Philip Alexander Cuadra

Alan Menezes

Matthew N Papakipos

Karim Abdalla

Robert T George

Andrew J Tao

Luke Durant

Sidong Li

Shun Wai Go

Brian S Pharris

Shailendra Singh

Manas Mandal

Arvind Gopalakrishnan

Steven E Molnar

Rui Manuel Bastos

Yury Y Uralsky

Wishwesh Anil Gandhi

Abbas Rashid

Tuan Anh Nguyen

John Stephen Montrym

Sean Jeffrey Treichler

Abraham Benjamin De Waal

Michael B Diamond

Christian Amsinck

Emmett Michael Kilgariff

Jeffrey A Bolz

Cass Watson Everitt

Philip Browning Johnson

Ronny Krashinsky

Daniel Elliot Wexler

Eric Sovelen Werness

Shirish C Gadre

Jack H Choquette

John H Edmondson

James M Van Dyke

Olivier Giroux

Rouslan Lyubomirov Dimitrov

Ignacio Llamas

David Kirk McAllister

Bryon S Nordquist

Manan Patel

Stephen Jones

Jonathan J Dunaisky

Christopher Frederick Lamb

Yan Yan Tang

John Erik Lindholm

Mark J Kilgard

John R Nickolls

James Michael O'Connor

John Matthew Burgess

Dale L Kirkland

Stephen Donald Lew

Michael C Shebanow

Alexander Lev Minkin

Naveen Cherukuri

Bengt-Olaf Schneider

Gregory Muthler

Paolo Enrique Sabella

Eric T Anderson

Peter B Holmqvist

Tyson J Bergland

Christian Rouet

Daniel P Wilde

Mark J French

Douglas Sim Dietrich

Roger L Allen

James Robertson

Nicholas Wang

James C Bowman

Richard A Silkebakken

Svetoslav D Tzvetkov

Gerald F Luiz

Adam Clark Weitkemper

Apparatuses, systems, and techniques to detect memory errors and isolate or migrate partitions on a parallel processing unit using an application programming interface to facilitate parallel computing, such as CUDA. In at least one embodiment, interrupts are intercepted and processed on a graphics processing unit indicating a memory error for one or more partitions, and a policy is applied to isolate that memory error from other partitions.

Techniques for memory error isolation

A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors in a virtualized environment

Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.

Virtualizing hardware processing resources in a processor

One embodiment of the present invention sets forth a technique for encapsulating compute task state that enables out-of-order scheduling and execution of the compute tasks. The scheduling circuitry organizes the compute tasks into groups based on priority levels. The compute tasks may then be selected for execution using different scheduling schemes. Each group is maintained as a linked list of pointers to compute tasks that are encoded as task metadata (TMD) stored in memory. A TMD encapsulates the state and parameters needed to initialize, schedule, and execute a compute task.

Compute task state encapsulation

A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Cooperative group arrays

Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

Distributed shared memory

A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Fault buffer for tracking page faults in unified virtual memory system

Techniques for reconfiguring partitions in a parallel processing system

Embodiments of the present invention set forth techniques for allocating execution resources to groups of threads within a graphics processing unit. A compute work distributor included in the graphics processing unit receives an indication from a process that a first group of threads is to be launched. The compute work distributor determines that a first subcontext associated with the process has at least one processor credit. In some embodiments, CTAs may be launched even when there are no processor credits, if one of the TPCs that was already acquired has sufficient space. The compute work distributor identifies a first processor included in a plurality of processors that has a processing load that is less than or equal to the processor loads associated with all other processors included in the plurality of processors. The compute work distributor launches the first group of threads to execute on the first processor.

Dynamic partitioning of execution resources

Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

PCIe traffic tracking hardware in a unified virtual memory system

Apparatuses, systems, and techniques for performing nested kernel execution within a parallel processing subsystem. In at least one embodiment, a parent thread launches a nested child grid on the parallel processing subsystem, and enables the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid.

Technique for computational nested parallelism

Growing community of inventors

Palo Alto, CA, United States of America

Jerome Francis Duluk, Jr