Cirrus Logic Inc.

General Electrodynamics Corporation

Crystal Semiconductor Corporation

Jerome E Johnston

Aryesh Amar

Axel Thomsen

Douglas F Pastorello

Edwin De Angel

Bruce Philip Del Signore

Kartik Nanda

Qicheng Yu

Saibun Wong

Rahul Singh

Sherry Xiaohong Wu

Dick E Davis

Charles R Brazell

Joe White

Donald Keith Coffey

Edwin Angel

Tommy B Molinar

A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

Circuits and methods for reducing the effects of level shifter delays in systems operating in multiple voltage domains

An analog-to-digital converter system comprises an analog-to-digital converter and a dither generator. The analog-to-digital converter receives an analog input signal and generates a digital signal that is proportional to the analog input signal. The output of the analog-to-digital converter is dominated by quantization error. The dither generator is responsive to a user-controlled input for generating an output signal. An adder sums the digital signal from the analog-to-digital converter with the output signal from the dither generator to provide a summed signal. The summed signal is either dominated by quantization noise or is properly dithered depending upon the user-controlled input.

Analog-to-digital converter with dither control

In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

Integrated circuit with mode control for selecting settled and unsettled output from a filter

Integrated circuit with a mode control selecting settled and unsettled output from a filter

An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

Application of a conditionally stable instrumentation amplifier to industrial measurement

A method and apparatus are used to process a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information. Command bits are set over a serial port input pin, and include at least one pointer bit indicative of a selected logical channel. In response to the command bits, the serial port controller sends signals indicative of the physical channel and the converter property specified in the selected logical channel to the ADC components.

Use of pointers to enhance flexibility of serial port interface for an integrated circuit with programmable components

A data clock pin SCLK may be used to receive an SCLK signal as well as sleep and reset signals. During normal operation, the SCLK input pin may receive the SCLK signal, a square wave type clock signal. However, the SCLK signal may also be coupled to a one-shot within the device. When signal SCLK is held high for a predetermined period of time, the one-shot is triggered and a SLEEP signal is generated. The device reacts to this SLEEP signal by entering a sleep mode. Similarly, if the SCLK signal is held low for a predetermined period of time, the one-shot may output a low level RESET signal. This RESET signal resets the device into an initial condition state. Other modes of operation, such as test modes and the like may be entered into by holding the SCLK signal high or low in conjunction with a predetermined logic level on another pin (e.g., VREF).

Single wire interface for an analog to digital converter

A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

Method and system for selecting implementation of a filter controller between a single conversion mode that ensures a fully-settled converted output and a continuous conversion mode

The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level. In the preferred embodiment of the present invention, a chip select signal {overscore (CS)} is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V&plus;supply voltage) or the low level logic signal voltage ({overscore (CS)}) to produce an output digital logic signal. In a further embodiment of the present invention, separate logic level signals IN and IN may be selectively switched by control logic to generate an output logic level signal independent of supply voltages V&plus; and V&minus;.

Definition of physical level of a logic output by a logic input

An analog-to-digital converter (ADC) architecture is fabricated on a semiconductor substrate which is negatively capacitively charge pumped below ground and subject to feedback regulation, rate measurements and adjustments. The ADC receives signal inputs of positive and negative polarity relative to ground, while being powered at 0V and 5V, without any negative power source input, as a result of a closed feedback loop which keeps the negative bias voltage constant as external supplies and component voltages vary. The high frequency pumping of the silicon substrate is subject to timing requirements which permit high resolution analog input signals to be converted in the presence of pump noise.

Synchronously pumped substrate analog-to-digital converter (ADC) system

A novel serial port interface system and method are disclosed. The serial port interface system achieves a three-pin interface mode with only a serial data input pin, a serial data output pin, and a serial clock pin by allocating a bit in an on-chip register to identify a three-pin conversion-done mode. In this three-pin mode, the serial data output pin signals an external device that data is ready to be accessed. Also disclosed with this three-pin conversion-done mode is a single conversion data read and a continuous conversion data read that may be selected through two separate bits in an on-chip register. In another aspect, a multiple register access capability is disclosed that allows multiple on-chip registers to be accessed with a single read/write command. This is accomplished by allocating a register select address in a command register to identify a group of registers, such as all of the set-up registers (gain, offset and configuration). An invalid command lock mode is also disclosed that places the serial port interface in a hold state, if an invalid command is decoded, to protect on-chip registers from corruption. Control of the serial port interface is removed from an external device until a specific restart sequence is applied.

Serial port interface system and method for an analog-to-digital

A microprocessor-based system (18) for weighing large objects, such as aircraft, at a number of points is disclosed. A plurality of load sensing units (10) each contain a strain gauges (50), analog amplification and calibration circuits (54), filtering circuits (56, 58), and analog-to-digital conversion circuitry (60). Each of the load sensing units (10) couple through serial data communication channels (14) to a controller (12), which contains a microprocessor (20), a keyboard (46), and a display (36). A microprocessor (20) executes a program which monitors all load sensing units (10), calculates weight based on data obtained from the load sensing units (10) and several compensation factors, and displays weight of a selected load sensing unit (10). Various foreground (200) and keyboard service (300) software routines are discussed.

Highly accurate weighing system

A platform weighing system (10) suitable for making accurate weight measurements of heavy objects, such as aircraft, is disclosed. Hardware and software combine to produce the accurate results. Analog hardware (14) includes hydraulic load cells (80a-80d), temperature sensing (91), filtering (90), and voltage-to-frequency conversion (104). Digital hardware (12) receives an oscillation signal output from the voltage-to-frequency conversion (104) and obtains load counts by monitoring the oscillation signal for consistent predetermined durations. The predetermined duration is chosen in software (226) to be immune to particularly pervasive noise signals. A microprocessor (16) converts load counts into a weight code which is output to a display (46). This conversion includes compensation for auto ranging (320), load cell excitation variance (282), temperature compensation (284), null offset variance (286), and zero drifting (304). In addition, nonlinearities in load cell output are compensated by linearly interpolating (288-296) between two of a plurality of calibration points that characterize the load cells (80a-80d ). Such compensations are performed primarily in software (200).

Growing community of inventors

Austin, TX, United States of America

Jerome E Johnston