International Business Machines Corporation

Kabushiki Kaisha Toshiba

Jerome D Harr

Karl R Hense

Shoichi Shimizu

Douglas W Gorgen

Robert W Donner

A variable gain amplifier has a plurality of amplifying stages. Each amplifying stage has a pair of cascode transistors that provide a low impedance path to signal currents when operating in the signal transmission mode and a high impedance to unwanted feedforward current when operating in a blocking mode. In a preferred embodiment, a pair of cascode transistors can also be shared among a plurality of amplifying stages of the variable gain amplifier. Further, when different pairs of input signals are provided to different amplifying stages, the circuit can be used as an analog multiplexer.

Variable gain amplifier or analog multiplexer with feedforward current

Switched pull down (SPD) ECL circuits have a switching circuit within the pull down portion of the output stage, so that a large portion of the total pull down current is switched to the negative going output node, and so that a small portion of the total pull down current is switched to the positive going output node. The negative going output node has a larger that normal ECL pull down current attached to it. The larger pull down current on the negative going node discharges the output capacitor in a shorter period of time. The shorter discharge time of negative going output results in a shorter fall delay time. Two smaller current sources are connected to each of the two differential ECL outputs to insure that both pull up transistors are forward biased so as to provide an adequate noise margin and insure correct circuit operation. Forward biasing the pull up transistors with a minimum acceptable amount of bias current at the emitters of the output pull up transistors provides proper immunity to noise.

Switched pull down emitter coupled logic circuits

Fast fall time for ECL logic waveforms are produced by use of a circuit, which very quickly transfers charge from the ECL output load capacitance into a temporary holding capacitor. The charge transferred onto the temporary holding capacitor may then be removed at a leisurely pace. The circuit includes a pulldown transistor, and a control circuit that selectively turns the pulldown transistor on, if the ECL output will be low, or off, if the ECL output will be high. The control circuit includes an emitter-follower transistor which follows the differential ECL collector node that changes voltage inversely to the desired final ECL output. A diode is connected to the emitter-follower transistor's emitter so that the diode output is two diode drops below the ECL collector node inverse in polarity to the output. The diode drives the base of the pulldown transistor, so that the base of the pulldown transistor remains static until the inputs to the circuit change.

Active pull-down circuit for ECL using a capacitive coupled circuit

A recording channel for a disk file including analog circuits implemented in integrated circuits whose frequency dependent parameters are controllable in response to the value of a control signal supplied to the circuit, as determined by a digital signal. In the preferred embodiment, the control signal to each analog circuit is from a digital to analog converter that is supplied with a digital signal from a register that is addressable and settable from a programmed microcontroller. Certain registers are able to be incremented or decremented by separate clock pulses and function as counters that are controlled by a signal in a feedback path separate from the microcontroller. Components external to the integrated circuits are, therefore, avoided while still maintaining the ability to adjust the analog read circuits to be responsive to data rates of different frequencies.

Recording channel with signal controlled integrated analog circuits

An adjustable filter arrangement is disclosed which is implemented in integrated circuit technologies. The filter configuration corresponds to a SALLEN-KEY filter in which the amplifier function is obtained by a transistor device, the R1 and R2 resistor functions are obtained by a first pair of suitably connected diodes, and the C1 and C2 functions are also integrated into the semiconductor chip. Adjustment of the natural frequency of the filter is obtained by the value of an externally supplied control current through the pair of diodes corresponding to R1 and R2. Adjustment of the damping characteristic of the filter is obtained by supplying a second control current to cause a relative change between the values of R1 and R2. No external components need be attached to the integrated circuit filter.

Integrated circuit filter with adjustable characteristics

This peak detecting circuitry avoids false peak indication while using component circuits of smaller dynamic range and lower voltage energizing power supplies than is possible with contemporary circuitry. The electric wave having peaks for which the times of occurrence are desired, is applied between an erecting (non-inverting) input terminal of a differential amplifying circuit and a point of fixed reference potential. A capacitor is connected between the inverting input terminal of the differential amplifier circuit and the reference point. The differential output of the amplifier circuit is applied through individual amplifier circuits to the capacitor for charging and discharging it in accordance with the instantaneous polarity of the electric wave. A unilateral impedor is interposed in the charging circuit in the form of a diode or a transistor for preventing discharge upon reversal of the electric wave slope. Latching and like circuitry is coupled to the detecting circuitry for indicating the detection. An electric connection, preferably including a diode element and/or a resistance element, is arranged between the indicating circuit and the amplifying circuit for dynamically altering the threshold from a high value as the peak of the wave containing noise is approached to a relatively low value as the peak of the wave containing timing information is approached.

Peak detecting circuitry and dual threshold circuitry therefor

The ideal response expected of an electromagnetic transducer, particularly of the Magneto-Resistive (M-R) type, obtains with signal translating circuitry for amplifying the varying signal produced and for dynamically biasing the transducer for maintaining the transducing operation in the linear portions of the characteristics of both the transducer and the amplifying circuitry. An M-R transducer is connected to the input circuit of alternating signal differential amplifying circuitry for delivering the desired signal at output terminals. The offset voltage across the transducer is compensated by differentially biasing input transistors of the amplifying circuitry. Biasing direct current through and/or voltage across the M-R transducer is controlled by a circuit connected to the output terminal and responsive to the signal thereat for developing a slowly inversely varying unidirectional voltage, preferably within a low pass filter interposed in the control circuit for stability. A current handling device, conveniently a transistor having the control voltage applied to a base electrode, is connected in series with the transducer for dynamically adjusting the unidirectional biasing current flowing therethrough.

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San Jose, CA, United States of America

Jerome D Harr