Ncr Corporation

Jerome Cohen

Peter C Chen

Ronald W Brower

A method of manufacturing a silicon gate MIS device providing automatic formation and alignment of the gate structure during formation of adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents-- typically oxide and silicon-- are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to a predetermined size beneath the overhanging mask. A deposition mask in the form of the photoresist mask or the gate silicon oxide and which is of the same size as the photoresist mask, is used to control the deposition of impurities within predetermined surface areas of the substrate which are spaced a predetermined distance from the silicon gate boundaries. By diffusion, the impurities are driven into the substrate to the desired depth to complete the source and drain, which are thereby driven laterally into coincidence with the gate boundaries. The aligned, non-overlapping relationship of the gate structure with the source and drain minimizes gate overlap capacitance.

Process for minimum overlap silicon gate devices

An adhesion-enhancing technique for preparing the surface of a polycrystalline silicon body to receive organic photoresist. In an exemplary procedure, the polysilicon is placed in an oxygen plasma chamber operating under rf power of about 90 milliwatts per cubic centimeter of chamber volume and a pressure of approximately 1 torr for 10 minutes to form an adhesion-enhancing oxide monolayer on the polysilicon.

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Centerville, OH, United States of America

Jerome Cohen