Institute for the Development of Emerging Architectures, L.l.c.

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Intel Corporation

Institute for the Development of Emerging Architecture L.l.c.

Jerome C Huck

Alan Hersh Karp

Roger A Golliver

Glenn T Colon-Bonet

Michael J Morrison

Dale Calvin Morris

Gautam B Doshi

Peter Markstein

William R Bryg

Carol Linda Thompson

Stephen G Burger

Guillermo Juan Rozas

Gary N Hammond

Jonathan Kent Ross

Judge K Arora

Sivakumar Makineni

Jack D Mills

James O Hays

Millind Mittal

Koichi Yamada

Rajiv Gupta

Blaine Douglas Gaither

Dean A Mulla

Michael L Ziegler

David Allen Fotland

Ruby B Lee

Benjamin Daniel Osecky

William S Worley, Jr

Barry J Flahive

Lawrence D K B Dwyer

Michael J Mahon

Verna Knapp

Sunil Saxena

Bernard L Stumpf

Martin J Whittaker

Daryl K Odnert

Ruby B L Lee

Guatam Bhawandas Doshi

Vivek S Pendharkar

Glen Colon-Bonet

Mike Morrison

Michael L Zi Gler

Jeff Kurtze

Example embodiments disclosed herein relate to touch screen selection. A device displays a plurality of touch elements on a touch-enabled display. The device receives a touch input via the touch-enabled display. Further, the device determines an ambiguity based on the touch selection input. The device magnifies an area associated with the touch selection input based on the ambiguity determination. Moreover, the area includes a set of the touch elements associated with the ambiguity termination. The device receives another touch input at the area via the touch-enabled display. Then, the device determines one of the touch elements based on the other touch input.

Touch screen selection

A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Method and system for enhancing computer processing performance

A method of converting an original code sequence to a modified code sequence where the original code sequence includes a procedure call that is prior to a load instruction that is configured to load a value into one of a first plurality of registers is provided. The method includes inserting an advanced load instruction associated with one of a second plurality of registers into the modified code sequence where the advanced load instruction is configured to cause the value to be loaded into the one of the first plurality of registers. The method also includes inserting the procedure call into the modified code sequence subsequent to the advanced load instruction and inserting a checking instruction associated with the one of the second plurality of registers into the modified code sequence subsequent to the procedure call.

Floating-point data speculation across a procedure call using an advanced load address table

A method for reducing cache memory misses in a computer that performs context switches between at least a first context and a second context. A First logic identifies a first prefetch region in a first memory element and a second logic identifies critical memory references within the first prefetch region during compilation of a computer program. The critical memory references within the first prefetch region correspond to data in cache memory if a context switch occurs from a process or thread associated with the second context to a process or thread associated with the first context during program execution. Third logic prefetches data associated with the identified critical memory references and stores the prefetched data in cache memory prior to a process or thread associated with the first context being resumed when a switch from the second context to the first context occurs during program execution.

Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch

A method for transferring data between a processor and a memory includes (A) executing, at the processor, an instruction that includes (i) a specifier of a location in a storage resource local to the processor, (ii) a specifier of an address in the memory, and (iii) a specifier of a size of a data block, (B) providing, from the processor to a controller, a set of control signals indicating (i) the address in the memory, and (ii) the size of the data block; and (C) transferring, by the controller, in response to receipt of the set of control signals, the data block atomically between the storage resource and the memory, without the processor having to first request a lock on the memory.

Atomic transfer of a block of data

A system of the present invention utilizes memory for storing a computer program and processing circuitry for processing and executing instructions of the computer program. In particular, the computer program includes a set of code and an unconditional branch instruction. The processing circuitry, in executing the computer program, receives run time data indicative of whether the set of code is enabled or disabled, and based on the run time data, the processing circuitry sets a value of a mode indicator. While the program is running, the processing circuitry receives and processes the unconditional branch instruction. When the set of code is disabled, the processing circuitry executes the unconditional branch instruction based on the mode indicator, thereby preventing execution of the set of code. However, when the set of code is enabled, the processing circuitry refrains from executing the unconditional branch instruction based on the mode indicator and executes the set of code. Thus, execution of the set of code is selectively enabled based on the status of the mode indicator.

System and method for selectively executing computer code

The system of the present invention utilizes memory for storing a computer program and processing circuitry for executing instructions of the computer program. In particular, the computer program includes at least one branch instruction and a set of code that is to be selectively enabled or disabled. The branch instruction includes an address identifier identifying a memory address to which the processing circuitry may branch when executing the branch instruction. The processing circuitry, in executing the computer program, receives run time data indicative of whether the set of code is enabled or disabled, and based on the run time data, the processing circuitry sets a value of a mode indicator. While the program is running, the processing circuitry executes the branch instruction. In executing the branch instruction, the processing circuitry, depending on the value of the mode indicator, branches to the address identified by address identifier or branches to a different address. The set of code is located at one of the foregoing addresses. Thus, execution of the set of code is either enabled or disabled by controlling the value of the mode indicator.

System and method for enabling selective execution of computer code

A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Methods and apparatus for controlling exponent range in floating-point calculations

A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

Emulated branch effected by trampoline mechanism

Atomic memory operations are provided by using exportable &ldquo;fetch and add&rdquo; instructions and by emulating IA-32 instructions prepended with a lock prefix. In accordance with the present invention, a CPU includes a default control register that includes IA-32 lock check enable bit (LC) that when set to &ldquo;1&rdquo;, causes an IA-32 atomic memory reference to raise an IA-32 intercept lock fault. An IA-32 intercept lock fault handler branches to appropriate code to atomically emulate the instruction. Furthermore, the present invention defines an exportable fetch and add (FETCHADD) instruction that reads a memory location indexed by a first register, places the contents read from the memory location into a second register, increments the value read from the memory location, and stores the sum back to the memory location. Associated with each virtual memory page is a memory attribute that can assume a state of &ldquo;cacheable using a write-back policy&rdquo; (WB), &ldquo;uncacheable&rdquo; (UC), or &ldquo;uncacheable and exportable&rdquo; (UCE). When a FETCHADD instruction is executed and the memory location accessed is in a page having an attribute set to WB, the FETCHADD is atomically executed by the CPU by obtaining exclusive use of the cache line containing the memory location. However, when a FETCHADD instruction is executed and the memory location accessed is in a page having an attribute set to UCE, the FETCHADD is atomically executed by exporting the FETCHADD instruction to a centralized location, such as a memory controller.

COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUCTION SHOULD BE EXECUTED USING CACHE COHERENCY OR BY EXPORTING THE EXPORTABLE INSTRUCTION, AND EMULATES INSTRUCTIONS SPECIFYING A BUS LOCK

Method and apparatus for storing and executing an instruction to load two independent registers with two values is disclosed. In one embodiment, a computer-readable medium is encoded with an instruction including an opcode field specifying that the instruction is an instruction to load two independent registers with a first value and a second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value; a second target register field specifying a second target register to load with the second value. A system to execute the instruction is also disclosed.

Execution of an instruction to load two independently selected registers in a single cycle

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A &ldquo;short format&rdquo; page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single &ldquo;long format&rdquo; page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2 bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2 bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.

Method and apparatus for calculating a page table index from a virtual address

Processor architecture having two or more floating-point status fields

The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.

System and method for deferring exceptions generated during speculative execution

A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.

Computer apparatus having special instructions to force ordered load and store operations

Growing community of inventors

Palo Alto, CA, United States of America

Jerome C Huck