Atmel Corporation

Jerome Alingry

Alain Vergnes

Sebastien Younes

A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of registers. A set of multiplexers has first data inputs coupled to the first set of registers, second data inputs coupled to the second set of registers, and select inputs. Logic circuitry is coupled to the output of the set of multiplexers and to the control inputs of the multiplexers, the control circuitry providing select information to the set of multiplexers and providing waveforms to the display panel to selectively display data from the first set of registers and the second set of registers in accordance with the select information.

Display controller operating mode using multiple data buffers

A display controller for providing signals to a discrete display panel unit comprising: a set of registers configured to hold data to be displayed; a first logic circuitry connected to the set of registers and configured to receive the data from the set of registers, generate the signal waveforms required by the display panel according to the data, and provide the signal waveforms to the display panel; a second logic circuitry connected to the first logic circuitry, the second logic circuitry configured to generate timing signals for timing the first logic circuitry providing the waveforms to the display panel; and a resistor ladder connected to the second logic circuitry, the resistor ladder configured to generate intermediate voltages required to drive the display panel, and configured to receive the timing signals, wherein the controller is configured to automatically and periodically disable the resistor ladder according to one of the timing signals.

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Aix en Provence, France

Jerome Alingry