Motorola Corporation

Jerome A Grula

Nicholas J Spence

Gary W Hoshizaki

Glen D Caby

James R Trent

Andrew Flint

A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory block macro (35) is built which includes a block of memory, precharge circuits, multiplexers, read/write multiplexers, and sense amplifiers. If multiple memory blocks are used a block deselect circuit (39) and row/block decoders (38) must be added to the memory block macro (35). A row and block deselection process is used in the SRAM architecture to simplify compilability and enhance speed.

Block architected static RAM configurable for different word widths and

A multichip module (10) having one or more IC die (12-18) supports JTAG testing with a plurality of registers (20-26) within each IC die. JTAG testing requires a one cycle delay bypass mode where registers within an IC not under test are bypassed. To support bypass mode when JTAG testing the multichip module on a printed circuit board, a bypass circuit around the multichip module provides the one cycle delay. The bypass circuit monitors the test data signals to the multichip module and enters bypass mode upon detecting a predetermined sequence of logic states during the instruction sequence. Otherwise, the test data signal passes through a plurality of registers within each IC die. The detection may be performed by counting logic states or otherwise monitoring in the instruction sequence.

Circuit and method of JTAG testing multichip modules

A data analyzer for use in BIST circuitry has been provided. The data analyzer allows both comparison analysis and signature analysis to be performed on a circuit response data stream. The data analyzer includes a plurality of data registers which are serially-coupled and where each data register is capable of performing comparison analysis and signature analysis on one data bit of the circuit response data stream. This allows the circuit under test can be completely and thoroughly tested for faults.

Enhanced data analyzer for use in bist circuitry

A BIST circuit that can be placed in a halt mode has been provided. During halt, the operation of the BIST circuit is stopped when an error has been detected thereby allowing for faster location of the error. The BIST circuit also includes a memory access mode which allows for independent read or write access to a predetermined address of a storage device under test.

BIST circuit with halt signal

A self-test that is variable to test an SRAM that is embedded on a semiconductor die is achieved. The self-test is performed by a modular self-test circuitry that can be varied to permit generating addresses, and data patterns for various SRAM architectures and sizes. An address block develops addresses which define a test location or test word within the SRAM. The address block also develops a time delay which is used during a data retention test. A data block develops test patterns that are written into SRAM test locations. The data block also analyzes data read from SRAM test locations or test words. Both the address block and the data block are formed by combining a number of individual address or data cells, thereby providing addresses and data patterns for a variety of different SRAM configurations. A control block operates the address block, the data block, and the SRAM to perform two memory tests. A fault analysis test identifies faults within and between memory locations, and a data retention test identifies memory retention errors.

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Chandler, AZ, United States of America

Jerome A Grula