International Business Machines Corporation

Jerome A Frankeny

Richard Francis Frankeny

Karl Hermann

Ronald L Imken

Javad Haj-ali-Ahmadi

James Robert Wilcox

Anthony P Ingraham

Keith Allan Vanderlee

James Steven Kamperman

Ronald E Hunt

Adolph B Habich

Danny E Massey

Terry F Hayden

Janet Louise Rice

Paul A Farrar

Joseph LaTorre

Thai Quoc Ngo

Rolf Wustrau

John A Williamson

Jacqueline A Shorter-Beauchamp

Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability. A multilayer composite laminar stackable circuit board structure is created using, as appropriate, layers having metallic cores and layers having capacitively configured cores. The multilayer laminar stackable circuit board provides direct vertical connection between surface mounted electronic components and the power, signal and capacitive decoupling layers of the composite board through the dendrites and joining metallurgy of the via and plug formations.

Laminar stackable circuit board structure with capacitor

A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors. Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The testing is performed at elevational temperatures. A test head structure is also disclosed.

Apparatus and method for burn-in/testing of integrated circuit devices

Test head for applying signals in a burn-in test of an integrated circuit

A socket for attaching a flip chip die or ball grid array devices to a printed circuit board substrate having a pattern of solder covered lands, with resources for removing the flip chip die or ball grid array device, resources for directly aligning the solder balls of the flip chip die or ball grid array device to the printed circuit board, resources for using an interposer of dendrite coated vias or pads to electrically and physically connect the solder balls of the flip chip die or ball grid array devices to the solder deposits of the printed circuit board, resources for having the interposer reconfigure the wiring for testing or replacement purposes, resources for utilizing the flexibility and resilience of the interposer to improve dendrite connections, and resources for heat sinking the flip chip die or ball grid array device by direct thermal contact. The socket applies an evenly distributed force to connect the aligned flip chip die or ball grid array device solder ball pattern to the underlying printed circuit board solder deposit pattern through dendrite penetration of the solder using an interposer situated between and aligned to each such solder pattern.

Socket for semi-permanently connecting a solder ball grid array device

Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability.

Method of making laminar stackable circuit board structure

Discrete computational elements are provided that will be connected to a base unit, and to one another or I/O devices, in order to configure a particular computer system. The base unit provides the electrical power required to energize the computational elements. A plurality of identically configured substrates are joined in a layered relation and are electrically connected with one another. These substrates are capable of being fabricated of different lengths such that they can extend outwardly from the computational element and may be connected to other computational elements. At least one integrated circuit will be placed on one side of the joined substrates and is electrically connected to each substrate layer. In this manner the ICs will be able to communicate with chips on other computational elements. A support member is also included that stiffens the plural substrate layers and independently distributes electrical power through voltage and ground potential planes, and interconnected substrate layers, to the chips. The support member will be disposed adjacent the substrate layers on a side opposite the ICs and independently attachable to the base unit by using electrical connection pins, a pluggable lip portion, or the like.

Modular component computer system

A memory module is built up from a power distribution assembly in the form of plates forming a capacitor of low inductance and a flexible circuit substrate. The circuit substrate is populated with precisely positioned contact pads for the power, read, write and address lines of memory chips that contact the substrate. Memory chips are fixed to heat spreaders and loaded into a chip holder which positions the chips for contact with the contact pads on the substrate. The substrate contact pads are plated to form dendritic crystals of palladium and the memory chips are provided with solder balls on the contact pads of the memory chip. The solder balls are held in contact with the contact pads by the compressive forces of clamping a heat sink over the heat spreaders for testing, and the assembly may be readily disassembled to replace any defective memory. The compression connection of the chips to the substrate may be relied on or the solder balls may be reflowed to establish permanent solder connections.

High density memory module

A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate.

Method for testing integrated circuits on a carrier substrate

A method of fabricating a substrate module is provided that includes cavities of a diameter and depth which take into account the statistical variance in the dimensions of C4 solder balls. By constructing cavities with the proper dimensions, electrical connection between the chip and substrate, via the solder balls, can be ensured. Further, an annular shoulder is provided which acts as a positive stop to prevent any over travel of the C4s within the cavity, thereby allowing a great deal more pressure to be applied to seat the chip than possible with conventional methods. The present invention also provides processes for applying a coating of material onto the substrate which acts as an adhesive and sealant. This material is provided intermediate any of the holes or cavities (vias) which may be contained within the substrate, and is not deposited in these vias such that no interference is encountered when attaching the chip by way of the C4 solder balls thereon. Chips, or additional substrate layers are then placed onto the substrate, thereby forming a sealed integrated circuit module, which has adhesive between the chip and carrier layers.

Chip attach and sealing method

A power management circuit for operating a magnetic repulsion punch comprising a storage capacitor arranged to be connected in parallel with an inductive load serving as an operating coil of the magnetic repulsion punch, a means for selectively and temporarily coupling the inductive load to the storage capacitor for forming a resonant circuit, and a means for charging the storage capacitor after each operation.

Power management circuit for a magnetic repulsion punch

This invention provides a heat sink assembly for cooling electrical and electronic circuits. A low cost assembly method is achieved by a pivotal assembly containing a heat sink which snaps into place adjacent to an electrical/electronic circuit which requires cooling. The snap-in heat sink assembly contains a resilient heat transfer material which is exposed to the devices requiring heat removal by windows or other openings in a plate which is disposed between the heat transfer material and the snap-in frame.

Pivotal heat sink assembly

A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate. This card can then be used in the manufacture of an electronic device without the necessity of reworking the burned-in ICs. Further, if any of the chips fail the burn-in testing, the time and overhead required for reworking is minimized since the chips are not permanently attached.

Growing community of inventors

Taylor, TX, United States of America

Jerome A Frankeny