Texas Instruments Corporation

Sperry Rand Corporation

Jerold A Seitchik

Stephen R Schenck

Thomas A Closson

David B Oxford

Thomas J Aton

Shivaling S Mahant-Shetti

Frank Scott Johnson

Sridhar Ramaswamy

Ekanayake Ajith Amerasekera

Scott D Jantz

Suran Ohnigian

Roger L Haggard

John Soji

T R Rao

A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formation, in a CMOS flow process, yet also provides for the bipolar junction transistor to be optimized.

One mask PNP (or NPN) transistor allowing high performance

An embodiment of the instant invention is a method of optimizing an I/O circuit formed on a substrate with regards to an overvoltage or ESD event wherein the I/O circuit comprises at least one MOS device which has I-V characteristics, the method comprising the steps of: extracting selective electrical characteristics of the MOS device while the MOS device is operating in the avalanche and snapback regions of the I-V characteristics of the MOS device; characterizing the MOS device for the overvoltage or ESD event based on the electrical characteristics of the MOS device under standard operating conditions, the MOS device being comprised of a parasitic bipolar transistor and the substrate having a resistance; and wherein the I/O circuit is optimized for the overvoltage or ESD events by modifying the I/O circuit based on the electrical characteristics of the MOS device in conjunction with the characterization of the parasitic bipolar transistor and the substrate resistance.

Method and system for extracting high current parasitic bipolar

A flash waveform analyzer (10) includes a transmission line (12) for propagating a signal from an input (14). The transmission line (12) contains a plurality of samplers (16) located at different points along the transmission line (12). Each sampler (16) is activated by a strobe pulse from a strobe source (18) in order to measure a characteristic of the signal at the different points along the transmission line (12). The propagation velocity of the signal is made slower than the propagation velocity of the strobe pulse by using a different dielectric constant in the transmission line (12) than that of the strobe delay line (17). The characteristic measured by each sampler (16) is sent to a multiplexer (20) that selectively outputs the measured characteristic from each sampler (16) to an analog-to-digital converter (22) for processing and subsequent analysis.

Flash waveform analyzer method and device

A system (10) is provided for approximating a nonlinear function. The system (10) comprises first and second multiple generating circuits (12) and (14) for multiplying a first quantity and a second quantity by up to three integer powers of two. First and second function generating circuits (16) and (18) generate first and second functions of the first and the second quantities by combining the multiples generated in first and second multiple generating circuits (12) and (14). First and second approximation generating circuits (20) and (22) generate first and second approximations of the nonlinear function by shifting the output of first and second function generating circuits (16) and (18). Approximation selecting circuit (24) outputs the appropriate approximation generated in first and second approximation generating circuits (20) and (22).

System and method for approximating nonlinear functions

A temperature compensated, phase tolerant sense amplifier for use in a magnetic bubble memory system in which current is applied to the detector resistors only during a bubble detect operation.

Magnetic bubble memory sense amplifier having a pulsed current mode of

Temperature compensated sense amplifier

Phase tolerant magnetic bubble memory sense amplifier

A method and apparatus are disclosed for detecting errors in a data set of sequential binary digits by initially separating alternating ones of the digits into data subsets and generating a cyclic redundancy code (CRC) for each data subset. After appending the CRC to the respective data subset to form corresponding code subsets, the code subsets are merged into a code set. To check for errors following any operation on the code set likely to introduce such errors, the code set is separated into the code subsets, each including the respective data subset CRC, and a CRC is generated on each code subset. Depending upon the form of the CRC generator, the code subset CRC value will indicate the presence of an error and, preferably, the location of such error. In the latter form, error correction can be conveniently performed as the data set is being reformed.

Method and apparatus for detecting errors in a data set

Temperature compensated magnetic bubble memory sense amplifier

There is disclosed herein a fault-tolerant memory organization which permits through the incorporation of redundancy the utilization of circuit chips having defective sections. The apparatus involves the use of redundant sections fabricated on the chip in conjunction with a data relocation technique. The relocation scheme utilizes a code-decode arrangement which inserts zeros into the data stream to avoid the defective sections and provides a zero delete arrangement when the previously coded information is retrieved.

Growing community of inventors

Dallas, TX, United States of America

Jerold A Seitchik