Intel Corporation

Silicon Hive B.v.

Jeroen Leijten

Joseph Williams

Kameran Azadet

Jay O'Neill

Eugene Scuteri

Harm Peters

Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

Processing pipeline with zero loop overhead

Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described. In one embodiment, a processor includes a single centralized circuit comprising an instruction decoder and a controller; and a plurality of circuit slices that each comprise an arithmetic logic unit, a multiplier, a register file, a local memory, and a same plurality of logic circuits and a packed data datapath in between, wherein each circuit slice includes a physical port that provides a unique identification value that identifies a circuit slice from the other circuit slices, and the controller is to broadcast a same configuration value to the plurality of circuit slices to cause a first circuit slice to enable a first logic circuit and enable a second logic circuit of the first circuit slice based on its unique identification value and the configuration value, and cause a second circuit slice to enable a same, first logic circuit and disable a same, second logic circuit of the second circuit slice based on its unique identification value and the configuration value.

Apparatuses, methods, and systems for vector processor architecture having an array of identical circuit blocks

A processor includes a memory and a decompressor. The memory is to store compressed instruction. The decompressor includes logic to receive a request for an instruction in the compressed instructions to be executed by the processor, determine a block in the memory including the requested instruction, and determine a start address of the block in the compressed instructions. The decompressor also includes logic decompress chunks of the block, a given chunk to include parts of a plurality of very-long instruction word (VLIW) instructions.

Instruction and logic for encoded word instruction compression

A memory controller performs DMA operations on arbitrary sized elements unbounded by the word size of the host memory or processor, which performs operations based on an element that represents an atomic data unit such as a pixel. In this manner, a corresponding coding effort is not concerned with computing and locating word boundaries and accommodating unused bits of data conventionally used for accommodating word boundaries on pixel data for video rendering, for example. An element in memory corresponds to a rendered atomic data item, such as a pixel. The controller determines an element precision indicative of a size of the element, and identifies a unit of memory based on a memory location and a packed representation of a plurality of the elements relative to the memory location. The unit has a height and width, defining elements arranged in a grid, and an element position is based on coordinates.

System and method for memory access

A digital signal processing system comprises a programmable processor (PROC) and a peripheral device (PD, MEM) coupled to the programmable processor via a burst generation device (BG). The processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element. The burst generation device (BG) groups a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively.

Growing community of inventors

Hulsel, Netherlands

Jeroen Leijten