Koninklijke Philips Corporation N.v.

Silicon Hive B.v.

Intel Corporation

Nytell Software LLC

Intel Benelux B.v.

Jeroen Anton Johan Leijten

Jan Hoogerbrugge

Alexander Augusteijn

Marco Jan Gerrit Bekooij

Adrianus Josephus Bink

Johan Sebastiaan Henri Van Gageldonk

Hendrik Tjeerd Joannes Zwartenkot

Bart Mesman

Willem Charles Mallon

Jozef Louis Van Meerbergen

Adwin Hugo Timmer

Yuanging Guo

Jürgen Von Oerthel

Erwan Yann Maurice Le Thenaff

Cornelis Arnoldus Josephus Van Eijk

Fran&ccedil;oise Jeannette Harmsze

A method for processing data using a time-stationary multiple-instruction word processing apparatus, arranged to execute a plurality of instructions in parallel, said method comprising the following steps: generating a set of multiple-instruction words (INS(i), INS(i+1), INS(i+2)), wherein each multiple-instruction word comprises a plurality of instruction fields, wherein each instruction field encodes control information for a corresponding resource of the processing apparatus, and wherein bit changes between an instruction field related to a no-operation instruction, and a corresponding instruction field of an adjacent multiple-instruction word are minimised; storing input data in a register file (RF, RF); processing data retrieved from the register file based on control information derived from the set of multiple-instruction words; disabling the write back of result data to the register file during execution of a no-operation instruction using a first dedicated no-operation code (ws, ws, wp, wp).

Lower power assembler

Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S), b) initializing a set of removed instructions as empty (S), c) determining the most compact representation of the first set of instructions (S) d) comparing the size of said most compact representation with a threshold value (S), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S), e2) removing said instruction having the highest coding cost from the first set of instructions and (S), e3) adding said instruction to the set of removed instructions (S), f) repeating steps b-f, wherein the first set of instructions is formed by the set of removed instructions (S, S).

Method and apparatus and record carrier

A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command.

Data processing circuit with a plurality of instruction modes for processing time-stationary encoded instructions, and method of operating/scheduling such data circuit

A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics.

Method and apparatus for designing a processor

A data processing circuit has an execution circuit () with a plurality of functional units (). An instruction decoder () is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (), and in the second instruction mode instructions control one functional unit. A mode control circuit () controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit () and the selection of destination registers from the set of registers (). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands. When instructions are scheduled, constraints are preferably imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. Such operations are avoided in an embodiment. In another embodiment, selected operations are scheduled for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by the execution of the jump command.

Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit

A multi-issue processor includes a register file and a plurality of issue slots, each one of the plurality of issue slots having a plurality of functional units and a plurality of holdable registers. The plurality of issue slots include a first set of issue slots and a second set of issue slots, and the register file is accessible by the plurality of issue slots. A location of at least a part of the plurality of holdable registers in the first set of issue slots is different from a location of at least a corresponding part of the plurality of holdable registers in the second set of issue slots.

Register systems and methods for a multi-issue processor

A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS, IS) arranged for parallel execution of the plurality of instructions; a register file (RF, RF) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV) on the validity of first result data (RD) produced by a first issue slot (IS) and a second identifier (OV) on the validity of second result data (RD) produced by a second issue slot (IS). The communication network comprises at least one selection circuit (SC) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.

Run-time selection of feed-back connections in a multiple-instruction word processor

A computer system with a processing unit and a memory. The processing unit is arranged to fetch memory lines from the memory and execute instructions from the memory lines. Each memory line is fetched as a whole and is capable of holding more than one instruction. An instruction comprises information that signals explicitly how the processing unit, when processing the instruction from a current memory line, should control how a part of processing is affected by crossing of a boundary to a subsequent memory line. The processing unit responds to the information by controlling said part as signaled by the information.

Variable length VLIW instruction with instruction fetch control bits for prefetching, stalling, or realigning in order to handle padding bits and instructions that cross memory line boundaries

Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use of instructions that require large immediate data, while simultaneously maintaining an efficient encoding and decoding of instructions. The processing apparatus comprises a plurality of issue slots (UC, UC, UC, UC), wherein each issue slot comprises a plurality of functional units (FU, FU, FU). The processing apparatus is arranged for processing data, based on control signals generated from a set of instructions being executed in parallel. The processing apparatus further comprises a dedicated issue slot (UC) arranged for loading an immediate value (IMV) in dependence upon a dedicated instruction (IMM). The immediate value (IMV) can be stored in a dedicated register file (RF) and the issue slot requiring this value can retrieve it from the dedicated register file (RF).

Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor

Computer architectures consist of a fixed data path, which is controlled by a set of control words. Each control word controls part of the data path. Each set of instructions generates a new set of control words. In case of a VLIW processor, multiple instructions are packaged into one so-called VLIW instruction. A VLIW processor uses multiple, independent functional units to execute these multiple instructions in parallel. Application specific domain tuning of a VLIW processor requires that instructions having varying requirements with respect to the number of instruction bits they require can be encoded in a single VLIW instruction, such that an efficient encoding and encoding of instructions is maintained. The present invention describes a processing apparatus as well as a processing method for processing data, allowing the use of such an asymmetric instruction set. The processing apparatus comprises at least a first (UC) and a second issue slot (UC), wherein each issue slot comprises a plurality of functional units (FU-FU, FU-FU). The first issue slot (UC) is being controlled by a first control word () being generated from a first instruction (InstrA) and the second issue slot is being controlled by a second control word () being generated from the second instruction (InstrD), the width of the first control word () being different from the width of the second control word (). By varying the width of a corresponding control word, instructions requiring a different number of bits can be efficiently encoded in a VLIW instruction while allowing an efficient instruction decoding as well.

Processing apparatus, processing method and compiler

A computer memory arrangement comprises a first plurality of input port facilities that are collectively coupled through a first router facility to selectively feed a first plurality of memory modules. It furthermore includes an output port facility that is fed collectively by the first plurality of memory modules. further ,the computer memory arrangement includes an access detection facility for detecting simultaneous and conflicting accesses occurring through more than one of the first plurality of input port facilities for a particular memory,module, and for thereupon allowing only a single one among the simultaneous and conflicting accesses while generating a stall signal for signaling a mandatory stall signal to any request source pertaining to another request.

Pseudo multiport data memory has stall facility

Programmable processors are used to transform input data into output data based on program information encoded in instructions. The value of the resulting output data depends, amongst others, on the momentary state of the processor at any given moment in time. This state is composed of temporary data values stored in registers, for example, as well as so-called flags. A disadvantage of the principle of flags, is that they cause side effects in the processor, especially in parallel processors. However, when removing the traditional concept of flags, the remaining problem is the implementation of branching. A processing system according to the invention comprises an execution unit (EX, EX), a first register file (RF, RF) for storing data, a memory (PM) and a second register file (RF) for storing a program counter. The execution unit conditionally executes dedicated instructions for writing a value of the program counter into the second register file. As a result, the processing system according to the invention allows conditional branching, without the use of flags.

Zero overhead branching and looping in time stationary processors

A computer memory arrangement comprises a first plurality of input port facilities () that are collectively coupled through a first router facility () to selectively feed a second plurality of memory modules (). It furthermore comprises an output port facility that is collectively fed by said second plurality of memory modules (). In particular, the computer memory arrangement comprises a detection facility () conflicting accesses through more than one of the first plurality of input port facilities, and for thereupon allowing only a single one among said simultaneous and conflicting accesses whilst generating a stall signal for signalling a mandatory stall cycle to a request source that implies an access latency thereto. The computer memory furthermore comprises a programming facility for having the access latency be selectably programmable according to an actual processing application.

Programmed access latency in mock multiport memory

The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means. Further, the present invention relates to a method for processing digital signals in a digital signal processing apparatus comprising a plurality of available hardware resource means, wherein at least a part of said hardware resource means execute operations under control of a first instruction set, and wherein at least a part of a predetermined limited subset of said plurality of available hardware resource means execute operations under control of a second instruction set having access to only said predetermined limited subset of said hardware resource means.

Interruptible digital signal processor having two instruction sets

A signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files. A plurality of different register files are selected based on a corresponding indication in said instruction word and the register address is supplied to said selected register files. Result values can be broadcasted to multiple registers in a single processor cycle while a copy operation between different register files is eliminated. Broadcasting is thus implemented via overlapping register address spaces, since physical registers having the same logical register address are provided in different register files.

Growing community of inventors

Eindhoven, Netherlands

Jeroen Anton Johan Leijten