Taiwan Semiconductor Manufacturing Comp. Ltd.

Jeremy Wu

Wei-Chia Cheng

Yu Jen Chen

Huan An Wu

This invention discloses a method of specifying pin states for a memory chip having one or more pins. In one embodiment of the invention, the pins are prioritized to obtain a pin order, wherein the pin state of a pin of a higher order dominates the pin state of a pin of a lower order. A number of possible combinations of the pin states are generated for the pins based on the pin order. The possible combinations are presented using a data presentation format. At least one pin of a higher order dominates at least one pin of a lower order when the at least one pin of a higher order is set in a predetermined pin state, such that the number of the possible combinations presented is reduced by neglecting combinations generated by the pins states of the dominated pins.

Method of specifying pin states for a memory chip

The invention creates a grid of horizontal and vertical lines across a plane, the plane is the plane in which metal-1 is to be created. This plane overlies an (underlying) layer of metal, such as metal of a basic cell component, to which interconnects must be established by the metal-1 pattern. By using the coordinates of the intersects of the horizontal and the vertical lines, these intersects can be assigned attributes that indicate whether a particular intersect should or should not be connected to the underlying layer of metal. Using these attributes of the intersects of the imaginary metal grid, an intersect that can be interconnected with the underlying layer of metal can now be extended beyond that intersect, making a maximum pattern available for interconnect to a pin type in the underlying layer of metal. After the pattern of metal-1 has been created in this manner over the complete surface of the underlying layer of metal (of for instance a cell), the created metal-1 pattern can be analyzed for potential rule violations.

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Xindian, Taiwan

Jeremy Wu