Seagate Technology Incorporated

Kioxia Corporation

Google Inc.

Spansion Llc.

Jeremy Werner

Erich Franz Haratsch

Earl T Cohen

Zhengang Chen

Ning Chen

Yunxiang Wu

Abdelhakim Alhussien

Leonid Baryudin

Krishna R Malakapalli

Joseph Charles Fjelstad

Wael Zohni

Suresh Rajan

David T Wang

Michael John Sebastian Smith

Yaron Klein

Philip Arnold Ferolito

Daniel L Rosenband

William P Schmidt

Ying Quan Wu

Jeremy Plunkett

Russell Barck

Kenichi Iwai

Various implementations described herein relate to systems and methods for transferring data from a source device to a destination device including receiving, by the destination device, a copy request from a host, performing, by the destination device, transfer with the source device to transfer data from buffers of the source device to buffers of the destination device, and writing, by the destination device, the data to a non-volatile storage of the destination device.

Systems and methods for data copy offload for storage devices

Various implementations described herein relate to systems and methods for providing data protection and recovery for drive failures, including receiving, by a storage device, a write request from a host operatively coupled to a storage device, and determining, by the storage device instead of the host, an XOR result by performing an XOR operation of new data and existing data. The new data is received from the host. The existing data is stored in the non-volatile storage.

Systems and methods for parity-based failure protection for storage devices

An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.

Flash memory read error recovery with soft-decision decode

An apparatus includes a storage medium with an opaque key storage and a controller. The controller may be coupled to the storage medium. The controller may be configured to (i) receive from a host device an authentication key, a plurality of I/O requests, and respective virtual media encryption keys associated with a number of the I/O requests, (ii) allow the host device to access the opaque key storage in response to the authentication key received from the host device being authenticated, (iii) generate a first media encryption key for a real band based upon the authentication key from the host device and key material stored on the apparatus, and (iv) generate a number of second media encryption keys for the number of I/O requests based on the first media encryption key and each of the respective virtual media encryption keys associated with each of the number of I/O requests.

Virtual bands concentration for self encrypting drives

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory.

Bad memory unit detection in a solid state drive

An apparatus having a memory and a controller is disclosed. The memory is configured to (i) program a protected lower unit in a lower page of a location, (ii) generate a corrected lower unit by correcting the protected lower unit using a first error correction code and (iii) program a protected upper unit in an upper page of the location based on the corrected lower unit. The controller is configured to generate the protected upper unit by encoding an upper write data item using a second error correction code. The controller is on a separate die as the memory.

On-die error detection and correction during multi-step programming

An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access. The controller includes an error correction engine configured to perform an error correction on codewords read from the non-volatile memory, and, if the error correction fails, to perform one or more retry procedures. The controller is further configured to perform one or more background procedures as a result of the error correction or one or more of the retry procedures not being successful and send an error message as a result of all of the retry procedures not being successful. The one or more background procedures are directed to determining a cause of the error correction failure.

Policy for read operations addressing on-the-fly decoding failure in non-volatile memory

An apparatus includes a storage device and a host device. The storage device may be configured to encrypt and decrypt user data during write and read operations, respectively. The host device is communicatively coupled to the storage device. The host device may be configured to execute the write and read operations by concentrating a first number of virtual bands into a second number of real bands, wherein said second number is smaller than said first number.

An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.

A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.

Retention detection and/or channel tracking policy in a flash memory based storage system

An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.

Error correction code rate management for nonvolatile memory

An architecture is presented that facilitates secure token generation and transmission capabilities in a mobile device. The system comprises at least one software application that includes a secure token assigned to a specific user and a memory module that communicates with an external processor. A security processor, non-volatile memory component and volatile memory component are integrated to form the memory module that communicates with the external processor. The memory module creates a secure execution environment for the execution of application agents associated with the software application and the secure token. The security processor of the system communicates with the software application and external processor to manage generation, authentication, confidentiality, and transmission of the secure token. And, the non-volatile memory allows the introduction of new tokens and the removal of old tokens.

Solid-state memory-based generation and handling of security authentication tokens

A system, method, and apparatus are included for providing additional space between an integrated circuit package and a circuit board. An integrated circuit package is provided including a plurality of integrated circuit package contacts. Also provided is a circuit board in electrical communication with the integrated circuit package. Further, the integrated circuit package, the integrated circuit contacts, and/or the circuit board is configured for providing additional space between the integrated circuit package and the circuit board to position at least a portion of at least one component between the integrated circuit package and the circuit board.

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San Jose, CA, United States of America

Jeremy Werner