Advanced Micro Devices Corporation

Jeremy Schreiber

Aaron Joseph Grenat

Benjamin Tsien

William Alexander Hughes

Eric M Rentschler

Kiran Bondalapati

Hao Huang

Timothy Russell Snyder

Pete J Hannan

Frank P Skowronski

Cory P Krug

Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

Method and circuitry for debugging a power-gated circuit

A power-gated retention flop circuit is disclosed. In one embodiment, a retention flop includes a first latch coupled to a first global voltage node and a virtual voltage node and configured to receive a data input signal, and a second latch coupled to receive the data input signal from the first latch, wherein the second latch is coupled to the first global voltage node and a second global voltage node. The second latch is configured to provide a data output signal based on the data input signal. A power-gating circuit is coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node. Thus, the first latch may be powered down while the second latch remains powered on.

Power-gated retention flops

A method and apparatus are described for providing timing information to a view placement interactive (VPI) tool user designing a multi-cell circuit. A circuit design comprising a plurality of cells is displayed to the user. Each cell includes a pre-characterized circuit structure. A graphical user interface (GUI) may be used to request a cell placement change, a design connectivity change or a cell type change. The circuit design is modified to implement the requested change, an incremental static timing analysis is performed, and the resulting timing information associated with the requested change is presented on the displayed circuit design. Timing information may be displayed directly on a cell that receives an output from the particular cell, and/or may be displayed adjacent to the particular cell. The timing information may include current and previous frequency slack information associated with each input and output pin of the particular cell.

Method and apparatus for providing timing information while designing a multi-cell circuit

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Austin, TX, United States of America

Jeremy Schreiber