Honeywell International Inc.

University of South Florida

Priatek, LLC

Honeywell Space Systems, Inc.

Jeremy Ramos

Scott D Stackelhouse

Ian A Troxel

Christopher J Butera

Jeffrey M Wolfe

David J Lupia

John R Samson

Srinivas Katkoori

Jason L Copenhaver

Gordon L Collyer

Jason Waltuch

Milind S Bharvirkar

Jason C Noah

Praveen K Samudrala

Systems and methods can support a prize-based digital advertising system. The system can receive advertising material associated with an offering from an advertiser. The advertising materials may be presented on one or more public display devices associated with a client system. Game play opportunities associated with the advertising material and the offering may be presented on the one or more public display devices. The client system can support game play by a user at the one or more public display devices. The user may be provided with a discount towards purchasing the offering. The user may also be provided the offering as a prize in response to achieving specified game play performance such as winning or placing within a tournament.

Prize-based digital advertising system

Systems, methods and devices are disclosed that provided for providing remote video feedback. The disclosure herein includes a transmitting computing device that is configured to produce an image frame encoded with metadata and to transmit the encoded image frame over a network to a remote display device. The remote display device includes a viewing screen contained in a chassis with bevel. The viewing screen includes an information validation pixel with the chassis extending over and covering the image validation pixel. The chassis also includes a photo sensor positioned on the under side of the bezel so as to be in operational view of the image validation pixel. The system also includes a sensor electronics module that is configured to detect the metadata when the metadata is displayed by the information content pixel and is received by the photo sensor. The sensor electronics module also generates image frame feedback information based upon the detecting. A remote computing device is included that is configured to receive the encoded image frame from the transmitting computer, render the encoded image frame upon the viewing screen and re-transmit the image frame feedback information to the transmitting computer from the sensor electronics module.

Image validation system for remote displays

An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.

Device and method to enhance availability of cluster-based processing systems

A method for detecting a single event functional interrupt for an electronic circuit is provided. The method involves periodically generating a refresh signal for the electronic circuit, and generating a single event functional interrupt indicator signal in the electronic circuit that is responsive to the refresh signal. The method also involves monitoring the single event functional interrupt indicator signal for a state that indicates a failed refresh attempt.

Single event functional interrupt detection system

An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.

Redundant processing architecture for single fault tolerance

An architecture for a reconfigurable network that can be implemented on a semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable network on a chip is disclosed, which includes aspects of reconfigurable computing, system on a chip, and network on a chip designs. More precisely, a reconfigurable network on a chip includes a general purpose microprocessor for implementing software tasks, a plurality of on-chip memories for facilitating the processing of large data structures as well as processor collaboration, a plurality of reconfigurable execution units including self-contained, individually reconfigurable programmable logic arrays, a plurality of configurable system interface units that provide interconnections between on-chip memories, networks or buses, an on-chip network including a network interconnection interface that enables communication between all reconfigurable execution units, configurable system interface units and general purpose microprocessors, a fine grain interconnect unit that gathers associated input/output signals for a particular interface and attaches them to a designated system interface resource, and a plurality of input/output blocks that supply the link between an on-chip interface resource and a particular external network or device interface. Advantageously, the network minimizes the configuration latency of the reconfigurable execution units and also enables reconfiguration on-the-fly.

Reconfigurable network on a chip

Methods and systems for assembling spacecraft in space are provided. A modular spacecraft comprises a plurality of spacecraft modules, wherein each spacecraft module includes one or more of bonding posts and receiving plates mounted to an exterior surface each spacecraft module, wherein the one or more bonding posts and receiving plates are adapted to form one or more of, an electro-weld bond and an adhesive bond, with the one or more receiving plates.

Systems and methods for semi-permanent, non-precision inspace assembly of space structures, modules and spacecraft

A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port communication device comprising a first port at which at least a portion of the raw payload data is written to the multi-port communication device and a second port at which at least a portion raw payload data written to the multi-port communication device is read by the reconfigurable processing element. The reconfigurable computer further includes a controller coupled to the reconfigurable processing element. The controller applies the configuration to the reconfigurable processing element and wherein the controller performs at least one single event upset mitigation operation.

Reconfigurable computing architecture for space applications

A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.

Growing community of inventors

Tampa, FL, United States of America

Jeremy Ramos