International Business Machines Corporation

Jeremy Paul Rowland

Michael Richard Ouellette

Michael Thomas Fragano

Steven Michael Eustis

Thomas B Chadwick, Jr

Rahul K Nadkarni

David J Wager

Krishnendu Mondal

Ciaran J Brennan

Jeffery Howard Oppold

Tarl S Gordon

Eric Jasinski

Neelesh Govindaraya Pai

Kevin M Tompsett

A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.

Method and apparatus for verifying memory testing software

A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element () during testing of a memory array (), and a method of repairing a memory array.

Enabling memory redundancy during testing

Methods and apparatuses for enabling a redundant memory element () during testing of a memory array (). The memory array () includes general memory elements () and redundant memory elements (). The general memory elements () are tested and any defective general memory elements () are replaced with redundant memory elements (). The redundant memory elements () are tested only when they are enabled.

An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.

Apparatus for testing a memory of an integrated circuit

A memory array for an integrated circuit includes a plurality of memory elements includes at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements. A failing address repair register is provided, having a register for controlling enablement of a corresponding redundant memory element and compare logic for determining whether an address of a failing memory element is stored in the register.

Memory array having a redundant memory element

A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into a RAM select register in the BIST. While the BIST performs a first testing pass for the first RAM, the tester collects cycle numbers of the failing cycles. Then, the BIST performs a second testing pass for the first RAM. At each failing cycle identified during the first testing pass, the BIST pauses so that the content of the location of the first RAM associated with the failing cycle and the state of the BIST can be extracted out of the memory chip. The testing procedures for the other RAMs are similar to that of the first RAM.

Memory testing

A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

Method and apparatus for test and repair of marginally functional SRAM cells

Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.

Self-test architecture to implement data column redundancy in a RAM

A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.

Method and apparatus of local word-line redundancy in CAM

A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

Method and apparatus for testing a write function of a dual-port static memory cell

A testing method and device for detecting the existence of &ldquo;stuck-open&rdquo;, faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.

Self-Test pattern to detect stuck open faults

A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.

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Savannah, GA, United States of America

Jeremy Paul Rowland