Seagate Technology Incorporated

Spansion Llc.

Lsi Corporation

Jeremy Isaac Nathaniel Werner

Earl T Cohen

Willy Obereiner

Timothy Lawrence Canepa

Leonid Baryudin

Joe Yuen Tom

Venkat Natarajan

Russell Barck

George Minassian

Karl David Schuh

Steven Gaskill

Hyun Soo Lee

Thad Omura

Sumit Puri

Aloysius C Ashley Wijeyeratnam

Karl Huan-Yao Ko

Mehdi Jazayeri

Kiran Madhav

Methods, systems and computer-readable storage media for requesting programming of N portions of a plurality of non-volatile memories (NVMs) in accordance with received data. Redundancy information sufficient to recover from failures of M of the N portions for which programming was requested is updated in response to the requesting programming. Upon identifying one to M of the N portions that have failed the programming, re-programming of the one to M of the N portions is requested in accordance with data calculated based at least in part on the redundancy information.

Non-volatile memory program failure recovery via redundant arrays

A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers of SSDs for production. The host writes the tests to an 'input' SMART log of each SSD, and each SSD writes results to a respective included 'output' SMART log. The commands include write drive, erase drive, SATA PHY burn-in, delay, and stress mode. The SSD MST capability is optionally used in conjunction with an SSD virtual manufacturing model.

Solid-state disk manufacturing self test

Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.

Non-volatile memory program failure recovery via redundant arrays enables higher programming bandwidth and/or reduced latency in some storage subsystem implementations, e.g. a solid-state disk. Data to program N portions of a plurality of non-volatile memories is received at a non-volatile memory controller. The data includes particular data to program a particular one of the N portions. The particular data is stored in an allocated buffer associated with the non-volatile memory controller. Programming the particular data to a particular one of the non-volatile memories is begun. Redundancy information sufficient to recover from failures of M of the N portions is updated. The allocated buffer is freed. At least one of the storing, the beginning programming, the updating, and the freeing is in response to the receiving of the particular data. The freeing is prior to the particular non-volatile memory completing the programming.

Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero 'index' as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.

Higher-level redundancy information computation

A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.

Dynamic higher-level redundancy mode management with independent silicon elements

Higher-level redundancy information computation enables a Solid-State Disk (SSD)controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero 'index' as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.

An architecture is presented that facilitates integrated security capabilities. A memory module is provided that comprises non-volatile memory that stores security software and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. Further, a host processor located outside of the memory module arbitrates with the security processor for access to the non-volatile memory. The memory module in communication with the host processor establishes a heightened level of security that can be utilized in authentication services and secure channel communications.

Secure co-processing memory controller integrated into an embedded memory subsystem

A machine implemented system and method that effectuates secure access to a flash memory associated with a mobile device. The system includes a security component that intercepts transactions between an external processor and the flash memory and implements authentication and access control to the flash memory. The system further includes components that can partition the flash memory and can associate authentication and access control information with the partitioned flash memory.

Multiple stakeholder secure memory partitioning and access control

An architecture is presented that facilitates maintaining a log of near field transactions in a memory module that includes security functionalities and near field communication (NFC) capabilities. The memory module comprises non-volatile memory that stores security software and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. The non-volatile memory is divided into partitions by the security processor. NFC radio frequency (RF) communication capabilities are integrated into the memory module such that the memory module directly interfaces to an external NFC antenna. This facilitates NFC communications within the secure environment of the memory module. Further, the memory module stores data related to near field transactions so that this data can be subsequently reviewed and exported in an appropriate format.

Non-volatile memory sub-system integrated with security for storing near field transactions

An architecture is presented that controls access to secure data via biometric verification. The system comprises a memory module that communicates with biometric data to establish a heightened level of security for controlling access to data stored in the non-volatile memory. The memory module includes a security processor, non-volatile memory, and volatile memory. The security processor provides for concurrent processing of security protocols, provides a secure execution environment within the memory module to evaluate and store biometric data, communicates with the biometric data sensors to fetch the biometric data, and analyzes the biometric data to control access to data stored in the non-volatile memory. Specifically, biometric data is input and communicated to the security processor, then compared against the existing biometric templates stored in the non-volatile memory. If the data matches, verification is sent to the external processor and the user is granted access to the secure assets.

Secure data verification via biometric input

An architecture is presented that facilitates integrating memory, security functionalities and near field communication (NFC) capabilities in a mobile device. A memory module is provided that comprises non-volatile memory that stores security software, sensitive data, and keys and a security processor that accesses the security software from the nonvolatile memory and performs security functions based on the security software stored. A NFC radio frequency transmitter and receiver (RF) is directly integrated into the security processor to facilitate NFC capabilities within the secure environment of the memory module. Further, the non-volatile memory directly interfaces to an NFC antenna positioned outside of the memory module via the integrated NFC RF. The integration of the security processor, memory, and NFC RF into the memory module provides a trusted environment for the manipulation and decryption of data received through the NFC antenna.

Near field communication, security and non-volatile memory integrated sub-system for embedded portable applications

Systems and methods that facilitate processing data and securing data written to or read from memory. A processor can include a host memory interface that monitors all bus traffic between a host processor and memory. The host memory interface can analyze commands generated by the host processor and determine the validity of the commands. Valid commands can proceed for further analysis; invalid commands can be aborted, for example, with the host memory interface and memory each set to an idle state. The host memory interface can analyze authentication information obtained via an authentication component, and information regarding memory partition rights, to determine whether a command partition violation exists as to the command. If a violation exists, the host memory interface can prevent the improper command from executing in the memory, and can cause a different operation to occur thereby allowing the memory to be placed in a known state.

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San Jose, CA, United States of America

Jeremy Isaac Nathaniel Werner