Qualcomm Incorporated

Jeremy H Lin

Hemanth Sampath

Ravi Palanki

Avneesh Agrawal

Arunava Chaudhuri

Raghu Narayan Challa

Da-shan Shiu

Iwen Yao

Alexei Yurievitch Gorokhov

Aamod Dinkar Khandekar

Tingfang Ji

Joseph Binamira Soriaga

Krishna Kiran Mukkavilli

Jing Jiang

Tamer Adel Kadous

Peter Pui Lok Ang

John Edward Smee

Parvathanathan Subrahmanya

Subramanya P Rao

Remi Jonathan Gurski

Jeong Geun Kim

Rajat Prakash

Sameer Vermani

Soumya Das

Bongyong Song

Edward Harrison Teague

Dominic Gerard Farmer

Gireesh Rajendran

Messay Amerga

Andrew Sendonaris

Chih-Ping Hsu

Christian Holenstein

Gangadhar Burra

Thomas Domenick Marra

Anup Savla

Kurt William Otte

MeeLan Lee

Thomas K Rowland

Gurdeep Singh

Sunil K Kandukuri Narayan

Kevin W Yen

Chalapathi Rao Emani

Joseph Victor Zanotelli

Min Wu

Mrinal Mahesh Nath

Ali RostamPisheh

Sunil Kumar Kandukuri Narayana

Megan Wu

Siddhartha Ray Chaudhuri

Meelan Lee

Parvathanathan c/o Qualcomm Incorporated Subrahmanya

Da-Shan Shiu

Aspects of the present disclosure provide a configurable bi-directional time division duplex (TDD) subframe structure. The configurable subframe structure includes a downlink control portion, an uplink control portion, an uplink data portion and a downlink data portion. A current subframe for communication between a scheduling entity and a set of one or more subordinate entities is produced by determining a desired ratio of uplink information to downlink information for the current subframe and configuring the configurable subframe structure with the desired ratio.

Configurable bi-directional time division duplex (TDD) subframe structure

One aspect of an apparatus for wireless communications is disclosed. The apparatus includes a controller, a first transceiver, and a second transceiver. The first transceiver is configurable by the controller to support first communications through a cellular network to at least one of a packet-based network and a circuit-switched network. The second transceiver configurable by the controller to operate with the first transceiver to support first communications through the cellular network in a first mode and support second communications through an access point to the packet-based network in a second mode. In an aspect, the second transceiver is further configured to switch from the first mode to the second mode by moving its wireless connection from the cellular network to the access point while maintaining a network-layer connection to the cellular network.

Case-based radio platform for wireless network

A system involves a transmitting device (for example, a first wireless communication device) and a receiving device (for example, a second wireless communication device). In the receiving device, LLR (Log-Likelihood Ratio) values are stored into an LLR buffer. LLR bit width is adjusted as a function of packet size of an incoming transmission to reduce the LLR buffer size required and/or to prevent LLR buffer capacity from being exceeded. The receiver may use a higher performance demodulator in order to maintain performance despite smaller LLR bit width. In the transmitting device, encoder code rate is adjusted as a function of receiver LLR buffer capacity and packet size of the outgoing transmission such that receiver LLR buffer capacity is not exceeded. Any combination of receiver LLR bit width adjustment, demodulator selection, and encoder code rate adjustment can be practiced to reduce LLR buffer size required while maintaining performance.

Method and system for LLR buffer reduction in a wireless communication modem

A communications system and method for a wireless mobile device is provided. The method includes performing sleep mode operations in a device and performing wake-up operations with one or more base stations in view of the sleep mode operations in the device. The method also includes demodulating a communications channel for the device during sleep mode operations in the device and prior to synchronizing with the base stations.

Efficient sleep mode operation for OFDMA systems

A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.

Wall clock timer and system for generic modem

An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Reuse engine with task list for fast fourier transform and method of using the same

Techniques for encoding and decoding data are described. In an aspect, multiple code rates for a forward error correction (FEC) code may be supported, and a suitable code rate may be selected based on packet size. A transmitter may obtain at least one threshold to use for code rate selection, determine a packet size to use for data transmission, and select a code rate from among the multiple code rates based on the packet size and the at least one threshold. In another aspect, multiple FEC codes of different types (e.g., Turbo, LDPC, and convolutional codes) may be supported, and a suitable FEC code may be selected based on packet size. The transmitter may obtain at least one threshold to use for FEC code selection and may select an FEC code from among the multiple FEC codes based on the packet size and the at least one threshold.

FEC code and code rate selection based on packet size

An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.

Buffered demod and demap functions

A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Reconfigurable wireless modem sub-circuits to implement multiple air interface standards

Off-line task list architecture utilizing tightly coupled memory system

A method and apparatus are presented for compensating drifts in access terminals occurring during a sleep time. The method includes determining whether a sleep time exceeds a threshold, buffering time domain samples containing acquisition pilots and a paging channel, powering down RF circuitry in the access terminal after buffering samples, processing the samples to compensate for drift, and determining whether the access terminal was paged based upon the processed samples. The apparatus includes a digital front end, an FFT engine coupled to the digital front end, a symbol buffer coupled to the FFT engine, a processor coupled to the digital front end, FFT engine, and symbol buffer, and a memory coupled to the processor, the memory further comprising instructions for executing the method.

Compensating for drifts occurring during sleep times in access terminals

A demodulation mask bitmap includes binary mask values. Each mask value corresponds to an input resource element to a demodulator. For each mask value of a first state, a demodulation engine of the demodulator is not clocked and the demodulator outputs a zero-valued resource element. For each mask value of a second state, the demodulation engine is clocked, the input resource element is demodulated, and the demodulator outputs a demodulated resource element. A demodulation mask bitmap is designed to mask pilot resource elements and corrupted resource elements. Power is conserved by not clocking the demodulation engine for corrupted and pilot resource elements. Subsequent LLR generation and decode operations are simplified. Decoder performance is improved because the decoder does not decode LLR values derived from corrupted resource elements and/or resource elements not relevant to the reconstruction of a communicated message.

Zeroing-out LLRs using demod-bitmap to improve performance of modem decoder

Techniques for segmented CDMA searching are disclosed. In one aspect, a searcher comprises a plurality of storage elements selectable for performing a plurality of segmentable search tasks, each storage element operable for storage of and access to state information for one of the plurality of search tasks. In another aspect, a first search task is interrupted in progress, the state information for the first task is stored, a second search task is performed, and the first search task is continued using the stored state information. In yet another aspect, a search task is segmented into smaller search segments, sized to fit within contiguous available time in the searcher. Various other aspects of the invention are also presented. These aspects have the benefit of circuit area and search-time efficiency which translate into reduced costs, increased standby time, increased acquisition speed, higher quality signal transmission, increased data throughput, decreased power, and improved overall system capacity.

Segmented CDMA searching

Growing community of inventors

Sunnyvale, CA, United States of America

Jeremy H Lin