Digital Equipment Corporation

Broadcom Corporation

Compaq Computer Corporation, Inc.

Jeremy Dion

Koray Oner

Robert A Eustace

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Descriptor-based load balancing

A computer implemented method is applied to convert a formatted document or text to an ordered list of words. The formatted document is first partitioned into first and second data structures stored in a memory of a computer. The first data structure stores text fragments, and the second data structure stores code fragments of the formatted document. Adjacent text fragments are concatenated to form possible ordered word lists. Possible words are matched against a dictionary of representative words. A best ordered word list having the fewest number of words is selected from the possible ordered word lists.

Extracting ordered list of words from documents comprising text and code fragments, without interpreting the code fragments

A computer implemented method analyzes an execution of a program. The method partitions the program into program components such as basic blocks and procedures. A source or executable representation of the program is instrumented to collect test coverage data. In addition, a flow graph representing the program components is generated. The program is then executed to collect test coverage data. Using the test coverage data and the flow graph, the program is partitioned into executed and unexecuted components. The number of instructions in each unexecuted program component is counted. Thus, a list of the unexecuted program components can be presented according to a decreasing order of the number of unexecuted instructions in the unexecuted program components.

Method for analyzing and presenting test execution flows of programs

For use with a multiprocessor system employing shared memory, a software controlled method maintains cache coherency and execution synchronization among processors. A processor executing a SEND instruction transfers a cache line to one or more processors executing a RECEIVE instruction in a synchronized manner. The processors also execute the SEND and RECEIVE instructions to synchronize the execution of iterations of a program loop whereby a control processor distributes indices of the iterations to be performed by each worker processor.

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Palo Alto, CA, United States of America

Jeremy Dion