International Business Machines Corporation

Jeremy Daniel Schaub

Fadi Hikmat Gebara

Hayden C Cranford, Jr

Volker Strumpen

Qiqing Christine Ouyang

John Patrick Keane

John Andrew Guckenberger

Guy M Cohen

Alfred Grill

Jack Oon Chu

Steven John Koester

Sani Richard Nassif

Alan J Drake

Jerry D Hayes

Gabriel Konrad Dehlinger

Joonsoo Kim

Russell Alan Budd

Michael R Tan

Jeannine Madelyn Trewhella

Young Hoon Kwark

Jeffrey Alan Kash

Robert Matthew Senger

Punit P Chiniwalla

Harmander Singh

Garry Trott

Alexander Reznicek

Casimer M DeCusatis

Tak H Ning

Kern Rim

Fei Liu

Min Yang

Daniel Michael Kuchta

Dennis L Rogers

Petar K Pepeljugoski

John D Crow

Christine Qiqing Ouyang

Qiging Ouyang

Casimer Decusatis

A method for monolithically integrating semiconductor waveguides, photodetectors and logic devices, i.e., field effect transistors, on a same substrate is provided. The method includes the use of a double semiconductor-on-insulator substrate that includes from bottom to top, a handle substrate, a first insulator layer, a first semiconductor material layer, a second insulator layer, and a second semiconductor material layer. The waveguides, photodetectors and logic devices can be formed in different regions of the substrate and are present atop a first insulator layer of the double semiconductor-on-insulator substrate.

Structure and method of integrating waveguides, photodetectors and logic devices

An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by the proximity of the requested values to the particular storage location. The cache supports multiple outstanding in-flight requests directed to the same address using an issue table that tracks multiple outstanding requests and control logic that applies the multiple requests to the same address in the order received by the cache memory. The cache also includes a backing store request table that tracks push-back write operations issued from the cache memory when the cache memory is full and a new value is provided from the external interface, and the control logic to prevent multiple copies of the same value from being loaded into the cache or a copy being loaded before a pending push-back has been completed.

Memory system including a spiral cache

A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.

Temperature-profiled device fingerprint generation and authentication from power-up states of static cells

A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

Test circuit for bias temperature instability recovery measurements

Systolic networks within a tiled storage array provide for movement of requested values to a front-most tile, while making space for the requested values at the front-most tile by moving other values away. A first and second information pathway provide different linear pathways through the tiles. The movement of other values, requests for values and responses to requests is controlled according to a clocking logic that governs the movement on the first and second information pathways according to a systolic duty cycle. The first information pathway may be a move-to-front network of a spiral cache, crossing the spiral push-back network which forms the push-back network. The systolic duty cycle may be a three-phase duty cycle, or a two-phase duty cycle may be provided if the storage tiles support a push-back swap operation.

Systolic networks for a spiral cache

A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.

Voltage comparator having improved kickback and jitter characteristics

An embedded photodetector apparatus for a three-dimensional complementary metal oxide semiconductor (CMOS) stacked chip assembly having a CMOS chip and one or more thinned CMOS layers is provided. At least one of the one or more thinned CMOS layers includes an active photodiode area defined within the one or more thinned CMOS layers, the active photodiode area being receptive of an optical signal incident thereon, and the active photodiode area comprising a bulk substrate portion of the thinned CMOS layer. The bulk substrate portion has a diode photodetector formed therein.

Embedded photodetector apparatus in a 3D CMOS chip stack

Testing is performed on an amplifier wafer housing a transimpedance amplifier prior to packaging the transimpedance amplifier with an external photodetector, wherein the transimpedance amplifier includes a small, auxiliary, integrated silicon photodetector provided at the input of the transimpedance, in parallel with external photodetector attachment points. To test the transimpedance amplifier, the transimpedance amplifier is stimulated by optically exciting the small auxiliary photodetector, wherein the small auxiliary photodetector is excited using short wavelength light, whereby advantages such as higher efficiency may be obtained. The testing method includes placing the amplifier wafer in a testing system, probing the power and ground connections on the amplifier wafer, illuminating the small auxiliary photodetector on the amplifier wafer, and detecting the output of the transimpedance amplifier housed on the amplifier wafer.

Testing of transimpedance amplifiers

Delay-based bias temperature instability recovery measurements for characterizing stress degradation and recovery

A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

System and circuit for determining data signal jitter via asynchronous sampling

The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector

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Austin, TX, United States of America

Jeremy Daniel Schaub