Intel Corporation

Santa Clara

Jeremy D Ecton

Brandon C Marin

Suddhasattwa Nad

Srinivas V Pietambaram

Kristof Darmawikarta

Oscar Ojeda

Leonel R Arana

Hiroki Tanaka

Aleksandar Aleksov

Arnab Roy

Yonggang Li

Gang Duan

Tarek A Ibrahim

Nicholas S Haehn

Bai Nie

Haobo Chen

Omkar G Karhade

Robert Alan May

Xiaoying Guo

Hsin-Wei Wang

Vahidreza Parichehreh

Ravindranath Vithal Mahajan

Nitin A Deshpande

Dilan Seneviratne

Xiaoqian Li

Changhua Liu

Hongxia Feng

Matthew L Tingey

Srinivas Venkata Ramanuja Pietambaram

Bohan Shan

Timothy White

Debendra Mallik

Rahul N Manepalli

Zhiguo Qian

Zhichao Zhang

Rahul Jain

Sai Vadlamani

Andrew James Brown

Xavier Francois Brun

Dingying David Xu

Praneeth Kumar Akkinepally

Jason M Gamba

Marcel Arlan Wall

Benjamin Duong

Shivasubramanian Balasubramanian

Divya Pratap

Chung Kwang Tan

Mohammad Mamunur Rahman

Sujit Sharan

Georgios C Dogiamis

Bryan K Casper

James E Jaussi

John Heck

Sri Ranga Sai Boyapati

Pooya Tadayon

Veronica Aleman Strong

Mitul Bharat Modi

Sheng C Li

Sri Chaitra Jyotsna Chavali

Mozhgan Mansuri

Ankur Agrawal

Frank Truong

Kyle Jordan Arrington

Bharat P Penmecha

Jung Kyu Han

Darko Grujicic

Sameer Paital

Arnab Sarkar

Hari Mahalingam

Eric J Moret

Jieying Kong

Kenneth Brown

Roy Dittler

Suresh V Pothukuchi

Kemal Aygün

Priyanka Dobriyal

Yue Deng

Sarah Blythe

Wei Wei

Xiaoxuan Sun

Rajesh Inti

Santosh Tripathi

Oladeji Fadayomi

Yiyang Zhou

Daryl Purcell

Jason Steill

Rajeev Ranjan

Susheel Jadhav

Whitney Bryks

Omkar Karhade

Nitin Deshpande

An electronic device comprises a photonic integrated circuit (PIC) including at least one waveguide, an emitting lens disposed on the PIC to emit light from the at least one waveguide in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a reflective surface configured to direct light emitted from the emitting lens in a direction away from the first surface of the PIC.

Photonic integrated circuit to glass substrate alignment through integrated cylindrical lens and waveguide structure

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Faraday rotator interconnect as a through-via configuration in a patch architecture

Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.

Position controlled waveguides and methods of manufacturing the same

Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

Hybrid bonding technologies with thermal expansion compensation structures

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Microelectronic assemblies including interconnects with different solder materials

Methods and apparatus to increase glass core thickness are disclosed. An example apparatus includes a first glass substrate, a second glass substrate, an interface layer between the first glass substrate and the second glass substrate, the interface layer coupling the first glass substrate to the second glass substrate, and an interconnect extending through at least a portion of the first glass substrate and at least a portion of the second glass substrate.

Methods and apparatus to increase glass core thickness

An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.

Glass interposer optical switching device and method

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Omni directional interconnect with magnetic fillers in mold matrix

Glass interposer optical resonator device and method

Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Airgap structures for high speed signal integrity

An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Electronic substrate having an embedded etch stop to control cavity depth in glass layers therein

An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

Angled inductor with small form factor

An integrated circuit device, comprising a substrate comprising a dielectric material and a conductor on or within the dielectric material of the substrate. The conductor comprises a first portion comprising a first sloped sidewall, wherein a first base width of the first portion is greater than a first top width of the first portion. The conductor also comprises a second portion over the first portion, the second portion comprising a second sloped sidewall, wherein a second base width of the upper portion is greater than both a second top width of the second portion and the first top width of the first portion.

Multi-step isotropic etch patterning of thick copper layers for forming high aspect-ratio conductors

Growing community of inventors

Gilbert, AZ, United States of America

Jeremy D Ecton