Sony Corporation

Sony Electronics Inc

Getchell Technologies LLC

Jeremy Chatwin

Takashi Masuda

Yosuke Ueno

Kenichi Maruko

Bernard James Griffiths

Zhiwei Zhou

Jacob Adams Wysocki

Omondi L Nyong'o

Mark A Readdie

Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.

System and method for processing data in an adder based circuit

A tri-state circuit that includes a control circuit coupled to a driver circuit. The driver circuit includes a first type of transistor connected in series with a second type of transistor. The control circuit receives an input data signal at an input data rate and a plurality of clock signals, and supplies a first signal and a second signal to the first type of transistor and the second type of transistor in response to the receipt of the input data signal. The control circuit further controls a tri-state switching operation of the first type of transistor and the second type of transistor such that the input data signal is selected and an output data signal is generated at an output data rate. The tri-state circuit is further utilized in other digital circuits, such as latch circuits, latch-based memory circuits or parallel-to-serial converter circuits to reduce inter symbol interference.

Digital circuit based on a modified tristate circuit

A magnetometer-based monitoring system comprising a magnet integrated with an object whose disposition is to be monitored, a first magnetometer secured in proximity to the object, and a second magnetometer secured at a fixed distance from the first magnetometer in proximity to the object. The monitoring system further comprising a processor to receive data from the first magnetometer and the second magnetometer, and calculate a measurement vector to determine the disposition of the object.

Magnet-based monitoring system

Various aspects of an injection-locked oscillator and method for controlling jitter and/or phase noise are disclosed herein. In accordance with an embodiment, an injection-locked oscillator includes one or more circuits that are configured to receive a pair of complementary phase output signals from one or more gain stages of the injection-locked oscillator. The one or more circuits may be configured to receive one or more switching signals. The received pair of complementary phase output signals are shorted by use of the one or more received switching signals. The shorting reduces the phase difference between an input signal and an output signal of the injection-locked oscillator.

Injection-locked oscillator and method for controlling jitter and/or phase noise

There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

Reception unit and receiving method

An apparatus for implementing a front end circuit for a transimpedance amplifier includes a front end core that receives an input signal from a photo diode. The front end core responsively generates a balanced output signal to downstream devices. A power supply provides a supply voltage to the front end circuit. In accordance with the present invention, a current source is located between the supply voltage the front end core to thereby isolate the front end core from disturbances on the power supply. This biasing arrangement advantageously provides an improved power supply rejection ratio for the front end circuit.

System and method for effectively implementing a front end for a transimpedance amplifier

A system and method for effectively performing a clock signal distribution procedure includes a clock generator configured to generate one or more clock signals that include electronic timing information. A clock load utilizes the electronic timing information from the clock signals to synchronize appropriate system processes. Capacitive coupling means are provided in a series configuration for transferring the clock signals from the clock generator to the clock load in accordance with an alternating-current direct-drive technique.

System and method for effectively performing a clock signal distribution procedure

An apparatus and method for effectively implementing a unit Gm cell includes an input P that receives an input P signal and an input N that receives an input N signal. The unit Gm cell further includes an output P that generates an output P signal that is connected through a first bias resistor to the input N. The unit Gm cell also includes an output N that generates an output N signal that is connected through a second bias resistor to the input P. The unit Gm cell features level-shifting resistors that cause the output P signal and the output N signal to be at different respective voltage levels. A Vcore supply voltage may thus be reduced by a voltage potential across the level-shifting resistors to operate the unit Gm cell with a reduced Vcore supply voltage.

System and method for effectively implementing a unit Gm cell

An apparatus for implementing a front end core for a transimpedance amplifier includes an input transimpedance stage that receives an FE core input signal and responsively generates an output transimpedance gain signal. A first output gain stage receives the output transimpedance gain signal and responsively generates an FE core output signal. A phase inverter stage also receives the output transimpedance gain signal and responsively generates an inverted output signal. A second output gain stage then receives the inverted output signal and responsively generates an inverted FE core output signal.

System and method for effectively implementing a front end core

A system and method for effectively utilizing a dual-mode phase-locked loop to support a data transmission procedure includes a voltage controlled oscillator that generates a receiver clock signal in response to VCO input control signals. A binary phase detector generates a BPD output signal during a BPD mode by comparing input data and the receiver clock signal. In addition, a lock-assist circuit generates a PFD output signal during a PFD mode by comparing a reference signal and a divided receiver clock signal. A loop filter performs a BPD transfer function to generate a VCO input control signal from the BPD output signal during the BPD mode. The same loop filter also performs a PFD transfer function to generate the VCO input control signal from the PFD output signal during the PFD mode.

System and method for implementing a dual-mode PLL to support a data transmission procedure

A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

System and method for implementing a phase detector to support a data transmission procedure

A system and method for effectively supporting a data transmission procedure includes a phase interpolator with a modular array of unit phase interpolators that each receives a respective input clock signal that is phase-shifted with respect to other input clock signals received by the remaining unit phase interpolators. The unit phase interpolators responsively generate corresponding UPI output signals that are summed together to produce a receiver clock signal. The phase interpolator receives a phase control word that includes a UPI selection segment and a UPI output-control segment. The phase interpolator utilizes the UPI selection segment to selectively activate pairs of the unit phase interpolators. The phase interpolator also utilizes the UPI output-control segment for controlling the UPI output signals to thereby adjust phase characteristics of the receiver clock signal.

System and method for utilizing a phase interpolator to support a data transmission procedure

Wide dynamic range and stability are achieved by adjusting a gain control resistance of an amplifier such that the pole ratio between the input and output is stable and by using a gain compensation technique to adjust output current. Adjustment of the gain is performed by determining a peak voltage between a gain stage and a dummy gain stage amplifier that does not amplify the input voltage. The peak voltage is compared to a gain control reference voltage and the comparison output is used to regulate both the variable gain and the gain compensation. The variable gain is performed using an FET variable resistor in a feed back loop of the amplifier. The gain compensation technique uses an FET variable resistor to adjust a voltage level of a driving transistor that adjusts an amount of current provided to an input of a current mirror. The mirrored current is then used to drain bias current from the amplifier.

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Santa Cruz, CA, United States of America

Jeremy Chatwin