Motorola Corporation

Silicon Laboratories Inc.

Texas Instruments Corporation

Pgs Geophysical As

Jeremy Charles Smith

Robert Alexis Peregrin Fernihough

Matthew Segsworth

Jeff Bowlus

Stephen G Jamison

Anirudh Oberoi

James W Miller

Gianluca Boselli

Vijay Kumar Reddy

Michael G Khazhinsky

John H Quigley

William E Moore

Percy V Gilbert

Shih W Sun

Yunfeng Xi

In an embodiment, an apparatus includes: a signal pad; a first diode having a first terminal coupled to the signal pad and a second terminal, the first diode having a first polarity; a second diode having a second terminal coupled to the signal pad and a first terminal, the second diode having a second polarity; a first insulated gate bipolar transistor (IGBT) having a first polarity, the first IGBT coupled between the second terminal of the first diode and a reference voltage node; and a second IGBT having the first polarity, the second IGBT coupled between the first terminal of the second diode and the reference voltage node.

High-voltage tolerant bi-directional electrostatic discharge protection circuit

A diode string for a semiconductor circuit configured with a guard ring silicon-controlled rectifier (SCR) for electrostatic discharge (ESD) protection. The diode string includes multiple NPN transistor diode structures formed in an N-well structure and electrically coupled in series between a reference voltage node and an I/O pad. Each diode structure may include a P-type retro-well structure including at least one N+ doped region and at least one P+ doped region. The P+ guard ring includes at least one P+ doped structure formed in the N-well structure disposed on either side of the first diode structure and electrically coupled to the reference voltage node. The P+ guard ring forms the SCR with the first diode structure. The diode string is triggered in response to an ESD event, which activates the SCR, and the SCR clamps the I/O pad to the reference voltage node and handles the ESD current.

Diode string configured with guard ring silicon-controlled rectifier for negative electrostatic discharge protection

Vented optical tube. At least some illustrative embodiments are conduits comprising a tube having a wall defining an interior volume of the tube. One or more optical fibers are disposed within the interior volume. The wall includes a plurality of vents passing from an outer surface of the wall to the interior volume, the plurality of vents disposed along a length of the tube, and wherein the vents are configured to convey a fluid in contact with the outer surface into the interior volume of the tube.

Vented optical tube

Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage Vthreshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage Vthreshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.

Dynamic trigger voltage control for an ESD protection device

Staggered Splices. At least some illustrative embodiments are apparatus including a tube having a wall defining an interior volume, first and second optical fibers disposed within the interior volume and the first and second optical fibers joined at a first splice. Also included are third and fourth optical fibers disposed within the interior volume, the third and fourth optical fibers joined at a second splice. The first splice and the second splice have an axially spaced-apart relationship within the interior volume of the tube.

Staggered optical fiber splices

At least some illustrative embodiments are including a method exposing a first optical fiber and a second optical fiber disposed within an interior volume of a first tube. A splice is formed between the first optical fiber and a third optical fiber, the splice joining an end of the first optical fiber and an end of the third optical fiber. A second tube is disposed the first, second, third optical fibers and the splice between the first and third optical fibers, wherein an end of the second tube adjoins an end of the first tube to form a structure comprising either an overlapping structure; or an abutting structure.

Tube reattachment

Diode string configurations are provided that employ one or more guard bars (G) positioned adjacent an end diode structure of a diode string to create a parasitic silicon-controlled rectifier (SCR) coupling between the end diode structure and the guard bar/s that operates to discharge current of an ESD event through a lateral parasitic bipolar transistor of the SCR and away from the individual diodes of the diode string. One or more of the disclosed guard bars may be positioned adjacent to a diode on a first end of a diode string to create a lateral SCR coupling for ESD discharge away from all of the diodes in the diode string without requiring positioning of a last diode on an opposite end of the same diode string adjacent the first terminal diode.

Diode string circuit configurations with improved parasitic silicon-controlled rectifier (SCR) conduction during electrostatic discharge (ESD) events

An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the first terminal and a power supply terminal and a second plurality of diodes arranged in series between the second terminal and the power supply terminal. The integrated circuit also includes a conductor configured to couple a first node within the first plurality of diodes to a second node within the second plurality of diodes. The first node is located between a first diode of the first plurality of diodes and a last diode of the first plurality of diodes, and the second node is located between a first diode of the second plurality of diodes and a last diode of the second plurality of diodes.

Electrostatic discharge protection circuit including a distributed diode string

Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.

Diode circuit layout topology with reduced lateral parasitic bipolar action

An electrostatic discharge (ESD) protection circuit apparatus is disclosed. The apparatus includes activation circuitry coupled to a first node. The activation circuitry includes a capacitor and a selectable load. A time constant &#x3c4; associated with the activation circuitry varies in accordance with the selectable load. The activation circuitry is configured to provide &#x3c4;=&#x3c4;for detection of an ESD event. A shunt is selectively enabled by the activation circuitry to short the first node to a second node in accordance with the detection of the ESD event. The activation circuitry is configured subsequent detection of the ESD event to provide &#x3c4;=&#x3c4;, wherein &#x3c4;&#x3e;&#x3c4;.

Electrostatic discharge protection rail clamp with discharge interruption circuitry

A circuit includes an input terminal and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode string formed from a plurality of P-N junction devices arranged in series. The diode string includes an input coupled to the input terminal and includes at least one output coupled to a power supply terminal. The circuit further includes a plurality of shunt elements. Each of the plurality of shunt elements includes a first terminal coupled to one of the plurality of P-N junction devices and a second terminal coupled to the power supply terminal. Each of the plurality of shunt elements is controllable to selectively couple the one of the plurality of P-N junction devices to the power supply terminal to distribute current flow across the diode string in response to an ESD event.

Circuits including a diode string comprised of bipolar stages having an adjustable pseudo beta for ESD protection

An integrated circuit includes a plurality of terminals, an unterminated diode string formed from a plurality of P-N junction devices arranged in series and coupled to the plurality of terminals, and a plurality of switches. Each of the plurality of switches includes a first terminal coupled to an anode of one of the plurality of P-N junction devices and a second terminal coupled to a power supply terminal, and is controllable to selectively couple the anode to the power supply terminal in response to an ESD event. The plurality of switches configured to dissipate an ESD current associated with the ESD event and dynamically terminate the unterminated diode string at a node where the ESD current falls below a turn-on threshold of a next P-N junction device in the unterminated diode string.

Circuit for ESD protection including dynamically terminated diode strings comprised of bipolar devices

Methods and systems are provided for determining efficacy of stress protection circuitry. The methods and systems employ a ring oscillator that models at least one parameter of a functional circuit to be protected by the stress protection circuit. A stress signal is applied to the ring oscillator and parametric degradation is measured to determine the effectiveness of the stress protection circuit in protecting the ring oscillator. A stress signal can be a voltage or current that stresses the normal operation of a functional circuit. The parametric degradation of the ring oscillator can be correlated to the parametric degradation that would be experienced by the functional circuit.

Methods and systems for determining efficacy of stress protection circuitry

Methods and circuits are disclosed for providing distributed ESD protection switchable between a capacitive decoupling state and an ESD protection state. The invention provides electronic circuitry with a selectable capacitive decoupling path and an ESD shunting path responsive to the detection of the presence or absence of an electrostatic discharge event. Circuits of the invention include one or more control circuits, electrostatic discharge devices, and control nodes operably coupled to responsively switch the circuit from a decoupling state to an electrostatic discharge state.

Local ESD power rail clamp which implements switchable I/O decoupling capacitance function

Electrostatic discharge protection circuitry includes a timing circuit operably coupled between the high supply side and low supply side of an associated circuit. The timing circuit has an RC node used for triggering a series of inverters configured to control an ESD dissipation device operably coupled to the high supply side node and the low side supply node of the circuit. A feedback transistor network and a feedback conditioning network is provided for ensuring that the ESD device is held on during an ESD event.

Growing community of inventors

Austin, TX, United States of America

Jeremy Charles Smith