Sonics, Incorporated

Facebook Technologies, LLC

Jeremy Chan

Doddaballapur N Jayasimha

Liping Guo

Drew Eric Wingard

Chien-Chun Chou

Timothy A Pontius

Kevin L Daberkow

Hervé Jacques Alexanian

Harutyun Aslanyan

Jay S Tomlinson

Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.

Reordering responses in a high performance on-chip network

A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router.

Credit flow control scheme in a router with flexible link widths utilizing minimal storage

A method for generating headers in packetized protocols for a flexible routing network for a Network on a Chip (NoC) architecture includes generating packets based on transmission traffic received from an initiator or a target connected to a routing network that connects disparate initiators and targets. Logic to generate the packets is in an interface located between the initiator or the target and the routing network. A header portion of a packet is variable in length and includes a header payload and header control information. Each of the header portion and the body portion includes one or more standard sized transmission units. The size of the transmission units and width of the header payload are determined by logic included in the interface. The width of the header payload is determined based on orthogonal groups with each of the orthogonal groups being associated with targets sharing an initiator thread.

Efficient header generation in packetized protocols for flexible system on chip architectures

A method for routing information in a flexible routing network which connects disparate initiators and targets includes implementing a packetization logic at an interface between an initiator or a target and a routing network to receive transmission traffic from the initiator or the target and to packetize the transmission traffic into packets. Each packet includes header and body portions. Each of the header and body portions includes one or more standard sized transmission units. Each standard sized transmission unit includes control and payload sections. A payload section associated with the body portion includes one or more chunks. The method includes encoding the one or more chunks using a Common Data Format (CDF). All transmissions within the routing network are based on the CDF. The CDF facilitates narrow-to-wide and wide-to-narrow link width conversion without having to manipulate subparts of data fields in the transmission traffic.

Use of common data format to facilitate link width conversion in a router with flexible link widths

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San Jose, CA, United States of America

Jeremy Chan