Micron Technology Incorporated

Jeremy Binfet

Kishore Kumar Muchherla

Akira Goda

Mark Alan Helm

Jeffrey S McNeil, Jr

Giuseppina Puzzilli

Gil Golov

Todd A Marquart

Carmine Miccoli

Niccolo' Righetti

Mark A Hawes

Liang Yu

Niccolo′ Righetti

Toru Tanzawa

Koji Sakui

Jonathan Scott Parry

Eric N Lee

Robert W Strong

William Richard Akin

Tommaso Vali

Walter Di Francesco

William C Filipiak

Sivagnanam Parthasarathy

Krishna Kumar Parat

Patrick Robert Khayat

Michele Piccardi

Lance W Dover

Sundararajan Sankaranarayanan

Qing Liang

Qisong Lin

Tejas Krishnamohan

Shuai Xu

Tyson M Stichka

Brian J Soderling

Arnaud A Furnemont

Violante Moschiano

James Fitzpatrick

Koichi Kawai

Luigi Pilolli

Daniel J Hubbard

Phong Sy Nguyen

Andrea D'Alessandro

Agostino Macerola

Suresh Rajgopal

Cristina Lattaro

Chulbum Kim

Jeremy Wayne Butterfield

Koichi Kawal

Claudia Ciaschi

Angelo Covello

Kishore Kumar Muccherla

A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

Peak power management priority override

In some implementations, a memory device may resolve a set of latches of a NAND page buffer to a set of initialized values. The memory device may obtain a NAND page buffer initialized data set from the set of initialized values of the set of latches. The memory device may generate a security key using the NAND page buffer initialized data set.

NAND page buffer based security operations

A memory device might include registers configured to store expected peak current magnitudes corresponding to a plurality of memory devices containing the memory device, and a controller configured to cause the memory device to determine whether to initiate a next phase of an access operation in response to at least a first sum of an expected peak current magnitude for the next phase of the access operation in a selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a first current demand budget, and a second sum of the expected peak current magnitude for the next phase of the access operation in the selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a second, lower, current demand budget.

Power management

A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

Scheduled interrupts for peak power management token ring communication

A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

Using duplicate data for improving error correction capability

A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Memory sub-system sanitization

In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.

Bit error management in memory devices

A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.

Program command generation with dummy data generation at a memory device

Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

Memory array reset read operation

A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

Partitioned memory having error detection capability

A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

Memories might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the memory to initiate an array operation on the array of memory cells, indicate an unavailability to initiate a next array operation, append a delay interval to an array access time of the array operation, and indicate an availability to initiate a next array operation in response to a completion of the delay interval. The delay interval might have a duration determined in response to an indication of temperature.

Apparatus and methods for thermal management in a memory

A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Memory plane access management

Growing community of inventors

Boise, ID, United States of America

Jeremy Binfet