Micron Technology Incorporated

Google Inc.

Jeremiah James Willcock

Timothy P Finkbeiner

Kyle B Wheeler

Glen Earl Hush

David L Pinney

Richard Cameron Murphy

Perry Victor Lea

Anton Korzh

George Kurian

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using dynamic minibatch sizes during neural network training. One of the methods includes receiving, by each of a plurality of host computer, a respective batch of training examples, each training example having zero or more features, computing, by each host computer, a minimum number of minibatches into which the host computer can divide the respective batch of training examples so that the host computer can process each minibatch using an embedding layer of the neural network without exceeding available computing resources, determining a largest minimum number of minibatches (N) into which any host computer can divide its respective batch of training examples, generating, by each host computer, N minibatches from the respective batch of training examples received by the host computer, and processing, by each host computer, the N minibatches using the embedding layer.

Dynamic minibatch sizes

A system and method for iteratively updating a parameter according to a gradient descent algorithm. In a given niteration of the method, one or more processors may determine a gradient value of a gradient vector of the parameter in a first dimension, determine a product value based at least in part on a sum of (i) the product value determined in an n−1iteration and (ii) a product of the determined gradient value and a learning rate of the gradient descent algorithm, determine an updated parameter value according to a function including the product value, and update the parameter to equal the updated parameter value.

Gradient descent algorithm for near-zero learning rate

A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. The processing unit then uses the sense amplifier and the accumulator to generate a first histogram of the set of data.

Histogram creation process for memory devices

The present disclosure includes apparatuses and methods related to mask patterns generated in memory from seed vectors. An example method includes performing operations on a plurality of data units of a seed vector and generating, by performance of the operations, a vector element in a mask pattern.

Mask patterns generated in memory from seed vectors

The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.

Computing reduction and prefix sum operations in memory

The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.

Apparatuses and methods for cache operations

The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component.

Data replication

The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of subarrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.

Apparatuses and methods for partitioned parallel data movement

Methods, systems, and apparatus, including an apparatus for generating clusters of building blocks of compute nodes using an optical network. In one aspect, a method includes receiving data specifying requested compute nodes for a computing workload. The data specifies a target arrangement of the nodes. A subset of building blocks of a superpod is selected. A logical arrangement of the subset of compute nodes that matches the target arrangement is determined. A workload cluster of compute nodes that includes the subset of the building blocks is generated. For each dimension of the workload cluster, respective routing data for two or more OCS switches for the dimension is configured. One-to-many switches are configured such that a second compute node of each segment of compute nodes is connected to a same OCS switch as a corresponding first compute node of a corresponding segment to which the second compute node is connected.

Reconfigurable computing pods using optical networks with one-to-many optical switches

The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. The memory device is configured to receive input corresponding to a data batch, where the input includes a designation that corresponds to the one of the plurality of designated subsets of memory cells to be conditionally updated, and to change a numerical value stored by the counter corresponding to the one of the plurality of designated subsets of memory cells.

Apparatuses and methods to change data category values

The present disclosure includes apparatuses and methods for operations using compressed and decompressed data. An example method includes receiving compressed data to a processing in memory (PIM) device and decompressing the compressed data on the PIM device.

Growing community of inventors

Boise, ID, United States of America

Jeremiah James Willcock