Dell Products Inc.

Jeremiah James Bartlett

Johan Rahardjo

Rama Rao Bisa

Pavan Kumar Gavvala

Joshua David Anderson

Timothy Michael Lambert

Sandor Tibor Farkas

Isaac Qin Wang

Jeffrey Leighton Kennedy

John Ross Palmer

Jordan Chin

Duk Moon Kim

Troy A Tiritilli

Aubreye Reddell

A system may include an air mover configured to drive a flow of air, a heat-generating component in a path of the flow of air, an assembly comprising heat-rejecting media and a thermoelectric cooling apparatus thermally coupled to the heat-rejecting media and arranged such that the heat-rejecting media is in the path of the flow of air between the air mover and the heat-generating component, and a thermal control system communicatively coupled to the thermoelectric cooling apparatus and configured to control an electrical parameter applied to the thermoelectric cooling apparatus in order to create a temperature gradient across the thermoelectric cooling apparatus, such that when the electrical parameter is applied to the thermoelectric cooling apparatus, heat is transferred from the flow of air to the thermoelectric cooling apparatus via the heat-rejecting media.

Systems and methods for thermal control of an information handling resource using thermoelectric effect

An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA programmed with accelerated function units (AFUs) to perform processing tasks for the processor. The AFUs include AFUs of a common type. A card BMC provides a temperature indication to the system BMC. The system BMC determines that a temperature of the FPGA add-in card exceeds a temperature threshold based upon the temperature indication, selects one of the common AFUs to be disabled, and directs the card BMC to disable the selected AFU. The card BMC disables the first AFU and not the second AFU in response to the direction to disable the first AFU.

System and method for power management of field-programmable gate arrays and load balancing of personality bitstreams from a baseboard management controller

An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

System and method for controlling a power-on sequence and power throttling using power brake

A first add-in card is connected to a second add-in card via a network communication link using a first network protocol. The first add-in card determines that a first network interface device is directly connected to a second network interface device via the network communication link, and directs that the first and second network interface devices communicate via a second network protocol based upon the first network interface device being directly connected to the second network interface device via the network communication link. The second network protocol transmits a higher proportion of data than the first network protocol.

System and method to provide heterogeneous protocols on network interface devices

The method may include: in a first measurement phase, generating a first input signal to the first input terminal of a leak detection cable interface circuit and receiving a first response signal in response the first input signal; in a second measurement phase, generating a second input signal to the second input terminal of the leak detection cable interface circuit and receiving a second response signal in response the second input signal; and based on at least the first response signal and the second response signal, determining a state of a leak detection cable communicatively coupled to the leak detection cable interface circuit.

Systems and methods for leak detection in liquid-cooled information handling systems

An information handling system includes a processor, and first and second field-programmable gate array (FPGA) add-in cards. The processor determines a configuration of the information handling system, the configuration defining architectural relationships among the first and second FPGA add-in cards and elements of the information handling system, determines that an accelerated function unit (AFU) performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card based upon the configuration, and programs the first AFU on the first FPGA card in based upon the determination that the first AFU performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card.

System and method for providing heterogeneous personality bitstreams on field-programmable gate arrays from a baseboard management controller

An information handling system includes a planar board and a peripheral interface device. The planar board includes a central processing unit, a baseboard management controller, and an interface logic circuit. The peripheral interface device includes a microcontroller and a serial communication interface device. The peripheral interface device is coupled to a peripheral device. The information handling system also includes an interconnect to couple signals from the planar board to the peripheral interface device. The interconnect includes a single wire to couple first information from the interface logic circuit to the peripheral interface device and to couple second information from the serial communication interface device to the interface logic circuit. The first information includes a first power control command.

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Austin, TX, United States of America

Jeremiah James Bartlett