Matsushita Electric Industrial Co., Ltd.

Jereld Pearson

Richard Sita

Edward Brosz

Shuji Inoue

Saiprasad V Naimpally

Hee-Yong Kim

Edwin Robert Meyer

Larry Phillips

Robert T Ryan

Ghanshyam Dave

Michael Iaquinto

A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which, when the decoder is operated in a first mode, decodes a Main Profile, High Level (MP&commat;HL) image to produce a high-definition video output signal and decodes a Main Profile, Main Level (MP&commat;ML) signal to produce a standard definition video signal. In addition, when the decoder is operated in a second mode, circuitry is used which generates a standard definition image from the MP&commat;HL signal. The video decoder includes a frequency-domain filter to reduce the resolution of the MP&commat;HL signal when the decoder is operated in the second mode.

MPEG decoder providing multiple standard output signals

A video memory system for storing ATSC video image data is configured as three channels, each channel having two banks and each bank including a plurality of memory rows. The exemplary memory system includes a buffer area for holding bit-stream data and six field buffer areas. The field buffer areas are arranged in pairs to form a three frame buffer areas, such that the buffer areas for the two fields in a given frame are allocated in respectively different banks. The video memory system includes an output memory controller which receives macroblocks of decoded image data and divides the received macroblocks into respective upper and lower half-macroblocks, the upper half-macroblock being stored in one field buffer of the frame and the lower half-macroblock being stored in the other field buffer of the frame. In addition, the output memory controller stores the luminance and chrominance components of the half-macroblocks in respectively different channels of the memory device and the channel assignment is changed from one half-macroblock to the next. The memory system also includes an input memory controller which retrieves reference half-macroblocks from the memory. The input memory controller is coupled to first and second address generators which operate concurrently to address image data in respectively different channels, banks and memory rows so that, when a reference half-macroblock which includes components from two or more stored half-macroblocks is retrieved, the memory read operations are overlapped.

Memory controller for an ATSC video decoder

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Mt. Ephraim, NJ, United States of America

Jereld Pearson