National Semiconductor Corporation

Jered Michael Sandner

Paul Joseph Kramer

Ohad Falik

The invention produces an output signal that maintains a substantially constant period corresponding to a clock signal. An input signal includes a period that is an integer multiple of the period of the clock signal. The timing or phase of the input signal may shift in comparison to the clock signal resulting in jitter. The invention detects and cancels the jitter by varying a delay between the input signal and the output signal. The delay corresponds to an integer multiple of the period of the clock signal such that a substantially constant period is maintained for the output signal. Alternatively, the intended period for the output signal may be adjusted to match a new period when a determination is made that a sufficient difference exists between the new period of the input signal and the intended period.

Apparatus and method for a jitter cancellation circuit

A serial stream interface for combining a master serial data stream comprising a sequence of N-bit master data packets and a slave serial data stream comprising a sequence of N-bit slave data packets. The serial stream interface comprises: 1) a slave input interface comprising a slave buffer having a serial input for receiving the slave serial data stream and an N-bit slave parallel output for outputting each of the N-bit slave data packets wherein the slave buffer stores each N-bit slave data packet using at least one slave timing signal associated with the slave serial data stream; 2) a source selection circuit having a first input channel for receiving an N-bit master parallel output from a first master data source and a second input channel coupled to the N-bit slave parallel output; and 3) a serialization circuit having an input coupled to an output of the source selection circuit for receiving a selected one of the N-bit master parallel output and the N-bit slave parallel output and a serial output, wherein the serialization circuit sequentially shifts out each bit of the selected one of the N-bit master parallel output and the N-bit slave parallel output.

Interface circuit for multiplexing multiple serial data streams from unsynchronized clock domains

A method and apparatus are arranged to provide a multi-bit digital signal that represents a normalized percentage of time that a signal is active. The apparatus includes an N-bit counter that is periodically reset to an initialization condition, and a logic block that processes the output of the N-bit counter. The N-bit counter is arranged to evaluate a monitored signal for each cycle of a clock signal, and modify the count accordingly. The logic block is configured to periodically scan the output of the N-bit counter after the expiration of a sampling time interval. The sampling time interval is determined by a timing circuit such as a window counter that is operated from the clock signal. The logic block periodically evaluates the output of the N-bit counter and provides the normalized multi-bit digital signal.

Signal active percentage monitor

A frequency divider circuit utilizes an asynchronous slip request signal to provide an output clock signal according to a programmable divide ratio &ldquo;R&rdquo;. A high frequency input clock signal has a frequency divided by a first factor to produce a divided signal when a slip signal is inactive. The output clock signal is produced by functionally dividing the frequency of the divided signal by a second factor. The second factor is determined by the programmable divide ratio divided by the first factor such that the frequency of the output clock signal is related to the frequency of the input clock signal and the programmable divide ratio. An asynchronous slip request signal is generated when the programmable divide ratio is a non-multiple of the first factor. The asynchronous slip request signal activates the slip signal such that a transition of the divided signal is skipped.

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Wellington, CO, United States of America

Jered Michael Sandner