Qlogic Corporation

Jerald K Alston

Bruce Anthony Klemin

Derek J Rohde

Sanjaya Anand

James Kunz

Rajendra R Gandhi

David Kwak

Kuangfu David Chu

Murali Rajagopal

Ali A Khwaja

Ting-Li Chan

Eric R Griffith

Oscar J Grijalva

Darren L Trapp

Henry Tran

Mark L Craven

A network device is provided. The network device includes a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving information complying with different protocols. The network device further includes a processor complex having a plurality of processors for processing information complying with different protocols and received by the plurality of ports; and a message queuing system (MQS) for managing messages for the plurality of processors regarding the received information complying with different protocols. Each processor can process information complying with any of the different protocols.

Systems and methods for sending and receiving information via a network device

Methods and apparatus for reducing power consumption in a host bus adapter (HBA) are provided. The methods include reducing a number of active lanes in an HBA link when link traffic is low, and increasing the number of active lanes when link traffic is high.

Power management for host bus adapters

Method and System for processing network information is provided. The system includes a computing system having a processor for executing instructions for an application module that generates an input/output ('I/O') request for transmitting and receiving network information to and from the network device; a storage driver for receiving the I/O request from the application module; a network protocol stack for executing a network protocol layer for processing network related information; and an accelerator module that interfaces with the storage driver and the network protocol stack for accelerating processing of Internet Small Computer System Interface (iSCSI) protocol data units (PDUs).

Method and system for accelerating network packet processing

A PCI-Express module that is coupled to plural host systems and to at least an input/output (I/O) device is provided. The PCI-Express module includes an upstream port module and a downstream port module that use a mapping table to facilitate the plural host systems sharing the I/O device by modifying a transaction layer packet (TLP) field. For upstream ID based traffic, a source identifier is replaced based on the mapping table and a destination identifier is replaced with a value that is captured during upstream port module initialization. For upstream address based traffic, the mapping table routes TLPs by using a downstream port number and a function number in a source identification field. For downstream ID based traffic, a destination identifier is replaced by using the mapping table for routing TLPs. For downstream address based traffic, the PCI-Express module uses an address map to route TLPs.

Method and system for sharing input/output devices

Method and system for an adapter coupled to a network via a network link is provided. The method includes using a first selectable mode and a second selectable mode to provide quality of service to a plurality of applications executed by one or more computing system. In the first selectable mode, the quality of service is based on allocating bandwidth of the network link and dynamically adjusting an initial priority assigned to a plurality of queues, each queue being associated with an application from among a plurality of applications. In the second selectable mode, the quality of service is based on a user assigning a priority to each of the plurality of applications and the adapter determines a number of input/output (I/O) requests it needs to process within a duration and then transfers information based on the determined number of I/O requests and the assigned priority.

Method and system for quality of service in host bus adapters

Method and system for an adapter operationally coupled to a host system and a network is provided. The adapter includes an internal memory that can be configured in a first mode to operate as a dedicated random access memory used by a main processor of the adapter; or configured in a second mode to operate both as a random access memory used by the main processor and also used for storing information received from the network. The method includes enabling the second mode of the internal memory so that the internal memory is configured to operate both as random access memory for the main processor and for storing information received from the network.

Method and system for storing frames in networks

Method and system for processing read requests sent by a network interface device to a host system is provided. The method includes sending staggered read requests within a programmable time interval ('T'), wherein a transmit direct memory access (DMA) module sends more than one read request to the host system within the time interval T; placing data received from the host system in response to the read requests in independent slots of a transmit buffer; and unloading the transmit buffer slots based on an unload command, wherein the unload command is based on a mapping of read requests corresponding to transmit buffer slot locations where data from the host system is stored, and data is sent from the transmit buffer to a network device in the same order as the read requests that are sent from the network interface device to host system.

Method and system for DMA optimization

A storage area network ('SAN') and a system is provided. The SAN includes, a host bus adapter operationally coupled with a credit extender, wherein the credit extender receives frames from a Fibre Channel network and sends the received frames to the HBA based on buffer space available in the HBA. The HBA notifies other Fibre Channel ports of buffer space available in the credit extender. The HBA sends a signal to the credit extender notifying the credit extender of available buffer space in the HBA. The HBA includes a management port for interfacing the HBA with the credit extender.

Method and system for using an in-line credit extender with a host bus adapter

An add-on card is provided for use within a computer system that has an expansion slot connected to a bus. The bus has a first supply line for supplying a first predetermined voltage and a second supply line for supplying a second predetermined voltage which is higher than the first predetermined voltage. The add-on card is adapted to operate properly regardless of whether the respective predetermined voltages are supplied on (1) the first supply line only, (2) the second supply line only, or (3) both supply lines. In a PCI bus implementation, where 3.3V and 5V are the predetermined voltage levels, the add-on card operates properly regardless of whether: only a 5V level is provided, only a 3.3V level is provided, or both 3.3V and 5V levels are provided.

Add-on card with automatic bus power line selection circuit

A state dependent synchronization circuit synchronizes an asynchronous input signal to a clock signal to generate a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also maintains the state of the output signal at a level corresponding to the input signal when the input signal does not change. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not charge state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal. The synchronizer preferably includes a first stage and a second stage. The first stage of the synchronizer isolates the second stage from any oscillation which may occur if the latched signal changes state too close to a transition in the clock signal. The first stage and the second stage of the synchronizer preferably operate on opposite edges of the clock signal. The circuit preferably includes a pair of cross-coupled gates that enable the circuit to recognize and synchrinize pulses of very short duration.

State dependent synchronization circuit which synchronizes leading and

A synchronization circuit synchronizes the transfer of pointer values from a transmitting circuit operating in a first clock domain to a receiving circuit operating in a second clock domain, wherein the first clock domain and the second clock domain are mutually asynchronous. An input latch operating in response to a first synchronization signal generated in the first clock domain transfers a pointer value to a latched pointer bus. The first synchronization signal is provided as an input to a synchronization section which generates a second synchronization signal in the second clock domain. The second synchronization signal enables an output latch to transfer the pointer value on the latched pointer bus to an output bus. The pointer value on the output bus is thus synchronized in the second clock domain. The second synchronization signal is then provided as an input to a synchronization section which generates the first synchronization signal in the first clock domain. The first synchronization signal initiates the transfer of the next pointer value to the latched pointer bus. The synchronization circuit operates alternately to generate the first synchronization signal in the first clock domain and the second synchronization signal in the second clock domain to latch a pointer value onto the latched pointer bus in the first clock domain and to output the pointer value from the latched pointer bus in the second clock domain.

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Coto de Caza, CA, United States of America

Jerald K Alston