Texas Instruments Corporation

Other

Jerald G Leach

Laurence Ray Simar, Jr

James F Potts

L Ray Simar, Jr

Alan Davis

Reid E Tatge

Surendar S Magar

Joseph A Coomes

Laurence R Simar

John C Cooper

Chein C Chen

David E Francis

Richard H Scales

Steve P Marshall

David Shippy

Mohammed N Maan

L Ray Simar Jr

Rakesh Pradhan

A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.

Processing devices with improved addressing capabilities systems and methods

Processor integrated circuit

A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ('ALU') L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. Execution unit S1 has circuitry for clearing or setting a designated bit field in a source operand in one execution phase of an instruction execution pipeline.

Microprocessor with an instruction for setting or clearing a bit field

A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ('ALU') L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. The microprocessor can execute an instruction which shifts a source operand a specified number of bits and saturates the result if a numerical overflow would result from the shift. Execution unit S1 has circuitry for saturating a destination operand by setting all bits within the destination to represent a most positive or a most negative number in a same single instruction execution phase in which the shift would have occurred if not for the overflow. The saturation circuitry examines the source operand prior to shifting to determine if the destination should be saturated.

Method and apparatus for performing a shift instruction with saturate by

A VLIW microprocessor capable of executing two or more instructions having data dependency in a single cycle. The microprocessor includes an instruction fetch and decode unit, a register file, and a plurality of execution units communicating with the instruction fetch and decode unit and with the register file. At least two of the execution units are connected such that the output of a first one of the two execution units is connected to the input of a second one of the two execution units, such that the output of the first execution unit is available as an input to the second execution unit during said single cycle, and such that both execution units can execute in said single cycle. In an exemplary embodiment, the first execution unit is a shift left unit, and the second execution unit is a shift right unit. With this embodiment, a complete extract operation can be performed in a single cycle.

Execution unit chaining for single cycle extract instruction having one

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus.

Data processing device with time-multiplexed memory bus

A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an arithmetic logic unit connected to the memory, operative to perform an arithmetic operation on data received by the arithmetic unit. An instruction decode and control unit connected to the memory, having an instruction register operative to hold a program instruction, is operative to decode a program instruction providing control signals to control the operations of the data processing device and to initiate a interrupt sequence responsive to an instruction code having a interrupt instruction. A program sequencer circuit connected to the memory, having a program register operative to hold a program counter corresponding to a program address is operative to access the memory with the program register to obtain the program instruction corresponding to the program address. A interrupt handler unit, connected to the instruction decode and control unit and the memory, having a hold register operative to store the program register, responsive to the control signals from the instruction decode and control unit to generate an intermediate address to access an interrupt counter from the memory, is operative to store the program register into the hold register and replace the program register with the interrupt counter wherein the interrupt counter corresponds to an address for accessing an interrupt instruction to execute an interrupt routine stored in the memory. Other devices, systems and methods are also disclosed.

Processing devices with look-ahead instruction systems and methods

An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Electrostatic discharge protection in integrated circuits, systems and

A video display processor and video display system which overlays mobile patterns called sprites over a background. For each horizontal line the video display processor reads from an external memory data corresponding to sprites appearing on that line. This sprite data is loaded into N sprite registers. For each pixel in the horizontal line a display priority logic selects for display either the highest priority sprite or a background display if that pixel includes no sprites. If there are more than N sprites for a particular horizontal line, then an additional sprite status flag is set. The additional sprite status flag may be read by a host processor via a processor port. Reading the additional sprite status flag resets the flag. Each sprite includes a sprite number. An additional sprite number register is loaded with the sprite number of the N+1st mobile pattern on the horizontal line. This additional sprite number register may be read by a host processor via a processor port. In the preferred embodiment, the additional sprite status flag, the additional sprite number register and a sprite coincidence flag consist of respective bits of a host processors readable status register.

Video display processor having indication of sprite in excess of the

A memory interface unit capable of coupling a microprocessor to memory external to the microprocessor, wherein the memory can be of at least two types differing in width, and where the data stored in such memory can be in different sizes, and wherein the memory can be formed in sections. The invention utilizes means for controlling at least two strobe signal lines and means for shifting the memory address lines, programmably, so as to accommodate the various combinations of memory width and data size.

Memory interface with address shift for different memory types

A memory interface unit for coupling a microprocessor to a memory external to the microprocessor, the memory being utilized for the storage of data therein and the retrieval of data therefrom, and the memory being provided in one or more memory banks, each of the banks being provided with a set of address lines and a byte enable line, data being transferring to and from each of the memory banks on a group of data lines, and the memory banks being provided in one or more banks whereby the group or groups of data lines, as the case may be, provide a memory data path having a physical transfer width for transfer of data to and from the memory, and the data being stored and retrieved over the memory data path in two or more data types, each type having a different size, the memory interface unit being provided with a set of address pins and a set of strobe pins, comprising. The unit includes a first element for providing an indication of a physical transfer width of a memory coupled to the memory interface unit. Also provided is a second element for providing an indication of a data type to be transferred to or from the memory. A third element, responsive to the first element and the second element, depending on the data type indication, provides to the address pins an address, shifted in position, with at least some of the address lines being for coupling to the address lines of the one or more banks of memory, as the case may be, and with one or more of the address pins being for activation of the byte enable line or lines, as the case may be, for data to be transferred, or, alternatively, providing to the address pins an address, unshifted in position, for coupling to the address lines of the one or more banks of memory, as the case may be, for addressing data to be transferred. Depending on the physical transfer width indication, the third element also causes one or more of the strobe pins to be used as additional address pins.

Growing community of inventors

Houston, TX, United States of America

Jerald G Leach