Motorola Corporation

Google Inc.

Freescale Semiconductor,inc.

Motorola Mobility LLC

Jerald A Hallmark

William J Ooms

Daniel S Marshall

Jun J Wang

Zhiyi Jimmy Yu

Jonathan K Abrokwah

Ravindranath Droopad

Robert Michael Gardner

Corey D Overgaard

Jamal Ramdani

Hossein Maleki

David J Anderson

Yang Wang

Ravi Droopad

Jay A Curless

Chenggang Xie

Jason N Howard

Jenn-Hwa Huang

Kurt W Eisenbeiser

Carl Lynn Shurboff

Alexander A Demkov

Jeffrey M Finder

Ellen Lan

Zhiyi Yi

An electrochemical cell assembly () includes a first cell and a second cell. The first cell can include a first anode () and a first cathode (), wound in a first jellyroll assembly () with a first jellyroll assembly exterior defined by the first cathode. The second cell can include a second anode () and a second cathode (), wound in a second jellyroll assembly () with a second jellyroll assembly exterior defined by the second anode. The first cell and the second cell can be arranged in a housing with the first jellyroll assembly exterior adjacent to the second jellyroll assembly exterior to improve energy density. The first cell assembly and the second cell assembly can have different widths to create differently shaped cell assemblies.

Stacked electrochemical cell with increased energy density

A method () of reducing variation of an energy storage capacity of a battery across its cycle life is disclosed. The method can include the step () of monitoring one or more voltages of one or more cells of a battery for a predetermined discharge usage time. Where a profile of the one or more voltages during the predetermined discharge usage time meets a predefined usage criterion, the method can include the step () of increasing a discharge voltage limit of the one or more cells. An energy management circuit () can be configured with a control circuit () operable to increase the discharge limit and to limit discharge of the cells when the discharge limit is reached.

Method and apparatus for improving cycle life capacity of a battery pack

A battery pack with reduced magnetic field emissions includes a plurality of cells () coupled electrically together by a first electrical conductor () and a second electrical conductor (). The first electrical conductor () couples positive terminals () to a terminal block (), while the second electrical conductor () couples the negative terminals () to the terminal block (). Each cell () contains an asymmetrical internal electrode construction () having electrical tabs () coupled to a cathode and anode. The cells () can be arranged with their corresponding asymmetrical internal electrode constructions () oriented in different directions to reduce magnetic field emissions. The first electrical conductor () and second electrical conductor () can be routed such that magnetic fields generated by discharge currents tend to reduce other magnetic fields produced by other components within the battery pack.

Electrochemical battery pack with reduced magnetic field emission and corresponding devices

Method and apparatus utilizing monocrystalline insulator

A fuel cell system is protected by monitoring at least one fuel cell parameter, comparing the parameter to a preset level, and disconnecting or reconnecting a main load in response to the fuel cell parameter. For example, a fuel cell system ( ) is provided with a protection circuit ( ) that prevents operation of the fuel cells in the negative dP/dI region. System ( ) includes a stack of fuel cells ( ) connected in series and coupled to a main load ( ). A controller ( ) provides a control signal ( ) based on the individual fuel cell voltage levels falling above or below a preset level. Control signal ( )is used to control a load switch ( )coupled between the stack of fuel cells ( ) and the main load ( ). The load switch ( ) disconnects the main load ( ) in order to prevent operation of the fuel cell cells in the negative dP/dI region.

Method and apparatus for fuel cell protection

High quality epitaxial layers of monocrystalline materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer ( ) on a silicon wafer ( ). The accommodating buffer layer ( ) is a layer of monocrystalline material spaced apart from the silicon wafer ( ) by an amorphous interface layer ( ) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits the fabrication of thin film pyroelectric devices ( ) on a monocrystalline silicon substrate.

Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same

A semiconductor structure comprises a silicon substrate ( ), one or more layers of single crystal oxides or nitrides ( ), and an interface ( ) between the silicon substrate and the one or more layers of single crystal oxides or nitrides, the interface manufactured with a crystalline material which matches the lattice constant of silicon. The interface comprises an atomic layer of silicon, nitrogen, and a metal in the form MSiN , where M is a metal. In a second embodiment, the interface comprises an atomic layer of silicon, a metal, and a mixture of nitrogen and oxygen in the form MSi&lsqb;N O &rsqb; , where M is a metal and X is 0&lE;X<1.

Semiconductor structure having a crystalline alkaline earth metal silicon nitride/oxide interface with silicon

A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.

Method and apparatus for creating a voltage threshold in a FET

A thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat including a condenser, a heat source, such as steam, and at least one thermoelectric module. The condenser includes a plurality of condenser tubes each having included therein a heat extractor. The heat source is in communication with the condenser and is characterized as providing thermal energy to the condenser. The at least one thermoelectric module, including a plurality of thermoelectric elements, is positioned in communication with at least one of the plurality of condenser tubes so that thermal energy flows through the thermoelectric elements thereby generating electrical power.

Thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat

A field effect transistor with an enhanced dielectric constant gate insulator including spaced apart source and drain terminals positioned on a substrate structure so as to define a gate area therebetween. A layer of laterally strained, enhanced dielectric constant dielectric material is epitaxially grown on the substrate structure in the gate area, and a gate metal is positioned on the layer of dielectric material to form a gate terminal in the gate area.

Enhanced dielectric constant gate insulator

A semiconductor structure comprises a silicon substrate (,), one or more layers of single crystal oxides (,), and an interface (,) between the silicon substrate and the one or more layers of single crystal oxides, the interface manufactured with a crystalline material which matches the lattice constant of silicon. The interface is an atomic layer of silicon, oxygen, and a metal in the form XSiO,, where X is a metal.

Semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon

A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (,) having a surface (,); forming on the surface of the silicon substrate an interface (,) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (,) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO,, where X is a metal.

Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon

A method of preparing crystalline alkaline earth metal oxides on a Si substrate wherein a Si substrate with amorphous silicon dioxide on a surface is provided. The substrate is heated to a temperature in a range of 700.degree. C. to 800.degree. C. and exposed to a beam of alkaline earth metal(s) in a molecular beam epitaxy chamber at a pressure within approximately a 10.sup.-9 -10.sup.-10 Torr range. During the molecular beam epitaxy the surface is monitored by RHEED technique to determine a conversion of the amorphous silicon dioxide to a crystalline alkaline earth metal oxide. Once the alkaline earth metal oxide is formed, additional layers of material, e.g. additional thickness of an alkaline earth metal oxide, single crystal ferroelectrics or high dielectric constant oxides on silicon for non-volatile and high density memory device applications.

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Gilbert, AZ, United States of America

Jerald A Hallmark