Samsung Electronics Co., Ltd.

Jeonil Lee

Jongmin Lee

Yeonjin Lee

Jimin Choi

Hyeonjin Shin

Youngjun Kim

Jinbum Kim

Kyung-Eun Byun

Yeonchoo Cho

Keunwook Shin

Seunggeol Nam

Janghee Lee

Minjung Choi

Juik Lee

Changseok Lee

Changhyun Kim

Junghoon Han

Alum Jung

Hyunseok Lim

Doosan Back

Gyuhyun Kil

Chansic Yoon

Sungjoo An

A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

Semiconductor devices having spacer structures

A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.

Semiconductor devices including a through-hole electrode

A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

Semiconductor device with crack-preventing structure

A method of pre-treating a substrate on which graphene will be directly formed may include pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.

Method of pre-treating substrate and method of directly forming graphene using the same

A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.

Semiconductor device including via structure and method for manufacturing the same

A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

Semiconductor device including through-silicon via and method of forming the same

A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

Semiconductor device including buried contact and method for manufacturing the same

A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

Thermal pad, semiconductor chip including the same and method of manufacturing the semiconductor chip

Provided are methods of directly growing a carbon material. The method may include a first operation and a second operation. The first operation may include adsorbing carbons onto a substrate by supplying the carbons to the substrate. The second operation may include removing unreacted carbon residues from the substrate after suspending the supplying the carbons of the first operation. The two operations may be repeated until a desired graphene is formed on the substrate. The substrate may be maintained at a temperature less than 700&#xb0; C. In another embodiment, the method may include forming a carbon layer on a substrate, removing carbons that are not directly adsorbed to the substrate on the carbon layer, and repeating the two operations until desired graphene is formed on the substrate. The forming of the carbon layer includes supplying individual carbons onto the substrate by preparing the individual carbons.

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Suwon-si, South Korea

Jeonil Lee