Skhynix Inc.

Lg Display Co., Ltd.

Jeongtae Hwang

Hyunsu Yoon

Youncheul Kim

Jeongsu Jeong

Kwanweon Kim

Yonggu Kang

Kwidong Kim

Changwoo Lee

Byungjae Lee

Igsoo Kwon

Yeonuk Kim

Jungho Lim

Nogeun Joo

Byeongchan Choi

A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command.

Semiconductor memory device and operating method thereof

The present disclosure provides a display device. The display device may comprise a display panel including a plurality of pixels, a reference current source providing a reference current, and a source drive IC including sensing units for sampling a signal input from the pixel through a sensing line and an ADC connected to the sensing units and obtaining sensing data related to a driving of the pixel. The source drive IC may further comprise a switch array connecting the sensing lines and the sensing units, and the switch array in each sensing unit may comprise a first switch for connecting a corresponding sensing unit to a first sensing line corresponding to the corresponding sensing unit and a second switch for connecting the corresponding sensing unit to a second sensing line adjacent and previous to the first sensing line or the reference current source.

Display device

A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Integrated circuit and memory device

This document relates to electrically compensating for display defects resulting from process error. A method of compensating for a display defect of a flat panel display comprises receiving position information indicative of a position of a display defect of a display panel and level information indicative of a degree of the display defect of the display panel, generating a reference gray level compensation value for compensating for the display defect based on the level information, storing the position information and the reference gray level compensation value in memory, and calculating compensation values for all gray levels by executing gamma point estimation (GPE) functions for expanding the reference gray level compensation value into all the gray levels based on received gain factor control information, modulating digital video data to be displayed in the display defect position by the calculated compensation values, and displaying the modulated digital video data in the display panel.

Method and an apparatus of compensating for display defect of flat panel display

A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.

Setting information storage circuit and integrated circuit chip including the same

An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit.

A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability.

One-time program cell array circuit and memory device including the same

A memory device includes a command decoder for generating a test selection code and a test setup data by decoding an external command and an external address, a non-volatile memory for storing an internal setup data, a counter for generating an internal selection code by counting a clock, a first selector for selecting the test selection code during a test mode operation, selecting the internal selection code during a boot-up operation, and transferring the selected selection code through a selection code transfer bus, a second selector for selecting the test setup data during the test mode operation, selecting the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transferring the selected selection code through a setup data transfer bus; and setup circuits for performing a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.

Growing community of inventors

Gyeonggi-do, South Korea

Jeongtae Hwang