Samsung Electronics Co., Ltd.

Jeongnam Han

Boun Yoon

Sangjine Park

Sukhun Choi

Kee-Sang Kwon

Wonsang Choi

Byung-Kwon Cho

Injoon Yeo

Kuntack Lee

Young-Hoo Kim

Yongsun Ko

Myung Geun Song

Jae-Jik Baek

Hayoung Jeon

Hagju Cho

Ki-Hyung Ko

Changki Hong

Myunggeun Song

Youngok Kim

Byungjae Park

Sangline Park

Wongsang Choi

Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

Semiconductor devices and methods for manufacturing the same

Semiconductor devices including an etch stop pattern and a sacrificial pattern with coplanar upper surfaces and a gate and a gap fill pattern with coplanar upper surfaces

A semiconductor device may include a pair of active patterns spaced apart from each other in a first direction, a pair of gate electrodes intersecting the pair of the active patterns in a second direction crossing the first direction, gate spacers on sidewalls of the pair of the active patterns, source/drain regions on the pair active patterns between the pair of the gate electrodes, and a spacer protection pattern between the pair of the gate electrodes and between the pair of the active patterns. The spacer protection pattern may be commonly connected to the gate spacers.

Semiconductor devices having spacer protection pattern

Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.

Semiconductor device and method of fabricating the same

A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Semiconductor device having dual metal silicide layers and method of manufacturing the same

A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.

Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same

Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Method for manufacturing semiconductor device having dual gate dielectric layer

A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Semiconductor device having metal plug and method of manufacturing the same

The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.

Wafer test method and wafer test apparatus

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Seoul, South Korea

Jeongnam Han