Samsung Electronics Co., Ltd.

Jeonglim Kim

Myungsoo Noh

Seulki Hong

Sunghwan Bae

Moongì Cho

Hyungjong Lee

Youngdeok Kwon

A semiconductor device includes a substrate; a guard ring disposed on the substrate and adjacent to an edge of the substrate; an integrated circuit structure surrounded by the guard ring and disposed on the substrate; and an insulating material structure disposed on a side surface of the guard ring, and wherein the guard ring includes a plurality of guard active structures on the substrate, a plurality of guard contact structures disposed on each of the plurality of guard active structures, and a guard interconnection structure disposed on a pair of guard contact structures adjacent to each other, among the plurality of guard contact structures, wherein each of the plurality of guard active structures includes a plurality of guard active fins spaced apart from each other.

Semiconductor device including guard rings

An integrated circuit device includes: a substrate including a fin type active region extending in a first direction; a gate structure intersecting the fin type active region and extending in a second direction perpendicular to the first direction; a source/drain region on sides of the gate structure; a gate isolation insulating layer contacting an end of the gate structure; a first contact connected to the source/drain region; and a second contact connected to the source/drain region, the second contact being longer in the second direction than the first contact, the second contact includes a first portion extending in the second direction from an area adjacent to one side of the gate structure beyond the end of the gate structure and facing a sidewall of the gate structure, and a second portion facing a sidewall of the gate isolation insulating layer, and the first portion is wider than the second portion.

Integrated circuit device and a method of manufacturing the same

In a method of manufacturing a photomask, a layout of a circuit mask pattern in a mask region corresponding to a chip region of a substrate is designed. A layout of a monitoring mask pattern representing a critical dimension (CD) of the circuit mask pattern in the mask region is designed. The monitoring mask pattern includes a mask-critical dimension uniformity (CDU) detection pattern configured to detect CDU in mask and a wafer-CDU detection pattern configured to detect CDU in wafer. A first optical proximity correction (OPC) is performed on the mask-CDU detection pattern. A second optical proximity correction is performed on the wafer-CDU detection pattern. A photomask having the circuit mask pattern and the monitoring mask pattern is formed.

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Seoul, South Korea

Jeonglim Kim