Samsung Electronics Co., Ltd.

Jeonghoon Ko

Changwook Jeong

Hyungtae Kim

Taehoon Kim

Jaehoon Jeong

Jongwon Kim

Hyojin Choi

In Huh

Jehyun Lee

Min-Chul Park

Jisu Ryu

Sanghoon Myung

Younsik Park

Sung-Bo Shim

Jaeho Jeong

Hyunjae Jang

Seungju Kim

Min Chul Jeon

Joonwan Chai

Yejin Jeong

Yunrong Li

A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

Proximity correction methods for semiconductor manufacturing processes

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Semiconductor fault analysis device and fault analysis method thereof

A method of inspecting patterns formed the manufacturing of semiconductor devices or the like includes producing an image of the patterns, producing a boundary image including a plurality of boundary patterns corresponding to first and second boundaries of each of the patterns, combining the pattern image and the boundary image to produce an overlapping image including overlapping patterns in which the patterns fill regions between the boundary patterns, and binarizing the overlapping image to produce a binary image including binary patterns corresponding to the overlapping patterns.

Methods of measuring patterns and methods of manufacturing semiconductor devices including the same

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Hwaseong-si, South Korea

Jeonghoon Ko