Apple Inc.

Jeonghee Shin

Harshavardhan Kaushikkar

Gregory S Mathews

Rohit Natarajan

Rohit Kumar Gupta

Srinivasa Rangan Sridharan

Peter A Lisherness

Mukul A Joshi

Amir Kleen

Sebastian Werner

Anjana Subramanian

Yu Simon Zhang

Techniques are disclosed relating to bandwidth compensation for certain memory traffic at high temperatures. In some embodiments, processor circuitry is configured to execute memory access operations for multiple traffic classes, including a first traffic class (e.g., real-time traffic) associated with a bandwidth quality-of-service parameter and a second traffic class (e.g., low-latency traffic). In some embodiments, memory controller circuitry is configured to access storage circuitry to perform the memory access operations, determine a temperature value associated with the storage circuitry, and, based on detection of a first temperature scenario for the storage circuitry, allocate memory access operations among the first and second traffic class according to a first allocation policy. In some embodiments, in response to detection of a second temperature scenario for the storage circuitry, memory controller circuitry allocates memory access operations among both traffic classes according to a second allocation policy. The second allocation policy may provide greater bandwidth for the first class than the first allocation policy.

Temperature-based bandwidth compensation for memory traffic

An apparatus includes a communication bus circuit, a memory circuit, a queue manager circuit, and an arbitration circuit. The communication bus circuit includes a command bus and a data bus separate from the command bus. The queue manager circuit may be configured to receive a first memory request and a second memory request, each request including a respective address value to be sent via the command bus. The first memory request may include a corresponding data operand to be sent via the data bus. The queue manager circuit may also be configured to distribute the first memory request and the second memory request among a plurality of bus queues. Distribution of the first and second memory requests may be based on the respective address values. The arbitration circuit may be configured to select a particular memory request from a particular one of the plurality of bus queues.

Arbitration sub-queues for a memory circuit

A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.

Bandwidth-aware fabric traffic shaping

Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

Communication channels with both shared and independent resources

Growing community of inventors

Sunnyvale, CA, United States of America

Jeonghee Shin