Samsung Electronics Co., Ltd.

Semicat, Inc.

Jeonghee Park

Changyup Park

Jiho Park

Hideki Horii

Kwangmin Park

Dongho Ahn

Jaeho Jung

Kyoung Sun Kim

Kihyun Hwang

Sanghoon Ahn

Sugwoo Jung

Zhe Wu

Jonguk Kim

Oik Kwon

Changhyun Cho

Hyun-Suk Kwon

Si-Ho Song

Hyeyoung Park

Wonjun Park

Jae Yeol Park

Jin Ho Oh

Jinwoo Lee

Gyuhwan Oh

Young-Min Ko

Heeju Shin

Dongsung Choi

Mansug Kang

Ja Bin Lee

ByeongJu Bae

Byongju Kim

Youngkuk Kim

Jungmoo Lee

Sukhwan Chung

Hwasung Chae

A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of InGeSbTe. In the phase change material layer of InGeSbTe, a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.

Semiconductor device including data storage material pattern

A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.

Resistive memory device

A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same

A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.

Three dimensional semiconductor memory devices

An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.

Apparatus for and method of fabricating semiconductor device

A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.

A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 &#x3bc;s to about 54 &#x3bc;s.

Method of fabricating a variable resistance memory device

A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.

A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.

Variable resistance memory device and method of fabricating the same

A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.

Variable resistance memory device

Disclosed are a collimator, a fabrication apparatus including the same, and a method of fabricating a semiconductor device using the same. The fabrication apparatus may include a chamber, a heater chuck provided in a lower region of the chamber and configured to heat a substrate, a target provided over the heater chuck, the target containing a source for a thin layer to be deposited on the substrate, a plasma electrode provided in an upper region of the chamber and configured to generate plasma near the target and thereby to produce particles from the source, and a collimator provided between the heater chuck and the target.

Collimator, fabrication apparatus including the same, and method of fabricating a semiconductor device using the same

A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.

Growing community of inventors

Hwaseong-si, South Korea

Jeonghee Park