Samsung Electronics Co., Ltd.

Jeongdon Ihm

Byunghoon Jeong

Jangwoo Lee

Seonkyoo Lee

Daehoon Na

Tongsung Kim

Taesung Lee

Kyungtae Kang

Chiweon Yoon

Junha Lee

HyunJin Kim

Dongho Shin

Youngjin Jeon

Anil Kavala

Jinman Han

Youngmin Jo

Jindo Byun

Kilsoo Kim

Jungjune Park

Kyoungtae Kang

Yoochang Sung

Kitae Park

Jaewoo Lee

Changsik Yoo

Bilal Ahmad Janjua

Yonghun Kim

Youngsun Min

TaeHyun Kim

Youngsoo Sohn

Jaemin Choi

Jinseok Heo

Seunghwan Hong

Yoo-Chang Sung

Hojun Chang

Manjae Yang

Jinhyeok Baek

Hwasuk Cho

ChaeHoon Kim

Changhyun Bae

Jiwan Jung

A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

Memory device and memory system including the same

Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

Frequency divider and memory device including the same

A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Nonvolatile memory device supporting high-efficiency I/O interface

A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

Semiconductor device including delay compensation circuit

A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

Memory device including interface circuit and method of operating the same

An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

Interface circuit, memory device, storage device, and method of operating the memory device

A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

Storage device and retraining method thereof

A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.

Receiver for cancelling common mode offset and crosstalk

An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

Interface circuit and operating method thereof to compensate for supply voltage variations

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

Impedance calibration circuit and memory device including the same

Growing community of inventors

Seongnam-si, South Korea

Jeongdon Ihm