Skhynix Inc.

Yonsei University

Jeongbin Kim

Eui-Young Chung

Hongil Yoon

KiTae Kim

Seungjin Lee

Kangwook Jo

Taehee You

Daehyung Cho

Minyoung Im

Kyungseon Cho

Kwangsu Kim

Byoung Jin Kim

Sang Hyup Lee

Disclosed are a memory system for a data swap and an operating method thereof. A memory system may include a plurality of layers coupled through at least one through silicon via (TSV) channel and a swap controller configured to generate a swap control command in response to a request received from an external host and to device swap data into a plurality of data units having a predetermined size to perform a swap operation between a first layer and a second layer among the plurality of layers, wherein the first layer and the second layer include at least one swap buffer and control a movement of the plurality of data units in response to the swap control command.

Memory system for data swap and operating method thereof

A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.

Method for designing an FPGA

A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.

Technology mapping method of an FPGA

A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.

Look up table including a nonvolatile memory element, FPGA including the look up table, and method for designing the FPGA

A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.

Look up table including magnetic element, FPGA including the look up table, and technology mapping method of the FPGA

Growing community of inventors

Seoul, South Korea

Jeongbin Kim