Hynix Semiconductor Inc.

Jeong-Yoon Ahn

Ji-Eun Jang

Young-Jun Ku

Beom-Ju Shin

Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Semiconductor device capable of suppressing a coupling effect of a test-disable transmission line

Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line

A semiconductor memory device includes a DLL for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amount corresponding to the delay control signal to generate a DLL clock signal; a clock counter reset signal generator for synchronizing an output enable reset signal with the external clock signal, delaying the synchronized signal by a delay amount corresponding to the delay control signal, and latching the delayed signal in response to the DLL clock signal to output a clock counter reset signal; and an output enable signal generator, reset in response to the clock counter reset signal, for counting the external clock signal and the DLL clock signal to generate an output enable signal corresponding to a read command and a CAS latency.

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Kyoungki-do, South Korea

Jeong-Yoon Ahn