Skhynix Inc.

Dongbu Hitek Co., Ltd.

Jeong Su Park

Yong Seok Oh

Joo Il Lee

In Mo Kwak

Myoung Soo Kim

Chang Moon Lim

Jun Taek Park

Hee Chan Shin

Jong Tack Jung

In Hwan Lee

Jae Youn Jang

Byoung Hoon Lee

Disclosed is a method of adjusting the performance of a wear leveling operation depending on the pattern of a workload according to a command inputted to a storage device, thereby managing a difference in the count of erase operations between storage areas included in a memory not to exceed a limit value and enabling a wear leveling operation to be performed.

Controller for improving wear leveling efficiency, storage device and method for operating storage device

Memory systems and methods of operating the memory systems are disclosed. A memory system including a plurality of data storage zones may comprise a memory device including a plurality of zones for storing data, and a memory controller configured to control the memory device in performing a write operation in the memory device. The memory controller is configured to, upon performing a write operation corresponding to a write request received from a host, update a logical write pointer and a physical write pointer associated with a zone that is targeted to perform the write operation corresponding to the write request received from the host, and upon performing a write operation corresponding an internal write command internally issued by the memory controller, update a physical write pointer associated with the zone that is targeted to perform the write operation corresponding to an internal write command issued by the memory controller.

Memory system and method of operating the same

A memory controller controlling an operation of a memory device includes a parity module configured to perform one or more exclusive OR operations using data to be stored in the memory device and generate parity according to the one or more exclusive OR operations, and a recovery controller configured to control the parity module to store the parity in the memory device based on the number of times the exclusive OR operation is performed.

Memory controller and method of operating the same

A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Power-supply device and electronic device including the same

A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.

Photomask and method for forming pattern of semiconductor device using the same

An image sensor and manufacturing method thereof are provided. A semiconductor substrate can include a light blocking region and a light receiving region. A photodiode can be formed in the light blocking region and in the light receiving region. A gate can be disposed at a side of the photodiode in the light receiving region, and a light blocking gate can be disposed on the photodiode in the light blocking region. A salicide layer can be formed on the light blocking gate.

Image sensor and a method for manufacturing the same

A CMOS image sensor and a fabricating method for a semiconductor device are disclosed. Embodiments provide a CMOS image sensor having an improved structure using a light reflection system, with a fabricating method thereof to simplify the fabrication process and maximize a light receiving area. Embodiments may be applied to a semiconductor device having a lamination structure.

CMOS image sensor and fabricating method thereof

A method for manufacturing a vertical CMOS image sensor related to a semiconductor device is disclosed. A high-temperature double annealing process and/or an additional passivation nitride film are selectively applied in order to improve dark leakage characteristics and also to prevent or reduce an incidence of circular defects, thereby enhancing the quality and reliability of the vertical CMOS image sensor.

Method for manufacturing vertical CMOS image sensor

A complementary metal oxide semiconductor (CMOS) image sensor including a semiconductor substrate having an inclined groove with an inclined surface and a light reception surface perpendicular to the semiconductor substrate, and a device forming area adjacent the light reception surface. A reflection film selectively formed on and/or over the inclined surface, a plurality of photodiodes substantially perpendicular to the surface of the substrate; and at least one MOS transistor formed on the surface of the device forming area.

Growing community of inventors

Seoul, South Korea

Jeong Su Park