Samsung Electronics Co., Ltd.

Jeong-Sic Jeon

Tae-hyuk Ahn

Jung-woo Seo

Kwang-Wook Lee

In-joon Yeo

Jong-Seo Hong

Jae-Woong Kim

Yoo-Sang Hwang

Chang-Jin Kang

Chun-Suk Suh

Jun-Sik Hong

Ji-hong Kim

Jin-Hong Kim

Chang-won Lee

Seung-Young Son

Hong-Mi Park

Young-sun Cho

Sang-Won Yeo

A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.

Methods of forming capacitors for semiconductor memory devices

Capacitors for semiconductor memory devices

An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.

Electronic devices including electrode walls with insulating layers thereon

A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.

Methods for forming DRAM devices including protective patterns and related devices

An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

Methods of forming electronic devices including electrodes with insulating spacers thereon

A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate

An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.

Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

Method of manufacturing a semiconductor memory device

Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

Semiconductor device having a contact window including a lower with a wider to provide a lower contact resistance

Electronic devices including electrodes with insulating spacers thereon

A method for fabricating a semiconductor device, including forming a gate insulating film and a gate electrode film on a semiconductor substrate, and patterning the gate electrode film to form a gate electrode. A portion of the gate insulating film is removed to form an undercut region beneath the gate electrode. A buffer silicon film is formed over an entire surface of the resultant substrate to cover the gate electrode and to fill the undercut region. The buffer silicon film is selectively oxidized to form a buffer silicon oxide film.

Method for fabricating a semiconductor device

Semiconductor device having a contact window including a lower region with a wider width to provide a lower contact resistance

Semiconductor device having a contact window and fabrication method thereof

Methods for fabricating semiconductor devices having capacitors are provided. A plurality of storage node electrodes are formed on a semiconductor substrate. Then, a capacitor dielectric layer is formed over the storage node electrodes. A plate electrode layer is subsequently formed on the capacitor dielectric layer. A hard mask layer is then formed on the resultant structure where the plate electrode layer is formed so as to fill a gap between the adjacent storage node electrodes. The hard mask layer and the plate electrode layer are successively patterned to form a plate electrode.

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Gyeonggi-do, South Korea

Jeong-Sic Jeon