Skhynix Inc.

Korea Advanced Institute of Science and Technology

Samsung Electronics Co., Ltd.

Georgia Tech Research Corporation

Jeong-Seok Ha

Dae-Sung Kim

Su-Hwang Jeong

Jaehong Kim

Steven W McLaughlin

Seung-Bum Suh

Sang-Ha Lee

Ji-Eun Oh

Sung Hoon Lim

Jae-Yoon Lee

Woo-Myoung Park

Jong-Bu Lim

Sung-Ho Chae

Seok-Jin Joo

Won-Jong Noh

Chol-Su Chae

Seok-Ju Han

Sang-Chul Lee

Myung-In Kim

Sang-Seok Yun

A controller is provided to include a processor reading data from a memory device, and a decoder receiving the data and decoding the data, the data being represented with check nodes and variable nodes. The decoder includes a check unit calculating syndrome values, a calculation unit receiving the decision values of the variable nodes and calculating flipping function values, a setting unit receiving the flipping function values and generating a candidate vector by dividing the flipping function values into groups and selecting at least some maximum values from the groups, the setting unit setting a flipping function threshold value, and a flipping unit receiving the flipping function threshold value, comparing the flipping function values of the variable nodes with the flipping function threshold value, and flipping a decision value of a target variable node having a greater flipping function value than the flipping function threshold value.

Controller and operating method for performing read operation to read data in memory device

A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

LDPC decoder, semiconductor memory system and operating method thereof

An operating method of a controller, comprising:

Controller, semiconductor memory system and operating method thereof

An operating method of a controller includes generating a square message matrix of k&#xd7;k; and generating an encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code, wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix, wherein the upper triangular matrix includes '&#x3b2;' numbers of message blocks, each of which has a size of '&#x3b1;+1', and &#x201c;(N&#x2212;&#x3b2;)&#x201d; numbers of message blocks, each of which has a size of &#x201c;&#x3b1;&#x201d;, and wherein &#x201c;&#x3b1;&#x201d;, &#x201c;&#x3b2;&#x201d; and N have relationships represented by equations 1 and 2:  where &#x201c;M&#x201d; represents a size of a message input from a host and &#x201c;N&#x201d; represents a number of message blocks forming the upper triangular matrix.

An operation method of a controller may include encoding a first data at a first code rate such that the encoded first data is decoded by a first parity check matrix included in a variable code-rate parity check matrix and encoding a second data at a second code-rate such that the encoded second data is decoded by a second parity check matrix included in a variable code-rate parity check matrix.

Controller and operating method thereof

An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal region in a matrix form; and performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region.

Memory controller, semiconductor memory system and operating method thereof

An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.

A memory system includes a memory device; and a controller suitable for encoding a message, storing the encoded message in the memory device and decoding the encoded message, wherein the controller is suitable for generating a message matrix including predetermined row codes and predetermined column codes symmetrical to the predetermined row codes, with the message or the encoded message using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BCH) code with a symmetrical structure.

Memory system and operating method thereof

The present disclosure relates to a pre-5-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4-generation (4G) communication system such as a long term evolution (LTE). A method for transmitting a signal in a signal transmitting apparatus in a communication system supporting a bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme is provided. The method includes performing an outer encoding operation; performing an interleaving operation on the outer code corresponding to an interleaving scheme which is based on a preset generation matrix to generate an interleaved signal; performing an inner encoding operation; performing a modulating operation; and transmitting the modulated signal, wherein the generation matrix is generated by applying at least one of a preset column permutation rule and a preset row permutation rule to a generation matrix for a quasi-cyclic (QC) interleaver.

Apparatus and method for transmitting/receiving signal in communication system supporting bit-interleaved coded modulation with iterative decoding scheme

The present disclosure relates to an apparatus and method supportive of distributed turbo coding based on relay network utilizing a noisy network coding scheme. For this, included is a relay node operating as a component encoder to relay a signal from a source node to a next node in a distributed turbo coding scheme. The relay node quantizes the signal transmitted from the source node and then interleaves the quantized signal using a predetermined pattern to distinguish the signal transmitted from the source node from a signal to be output from an opposing node, so that the signal transmitted from the source node is relayed to the next node based on a noisy network coding scheme.

Distributed turbo encoder and method

An operation method of a flash memory system includes a hard decision decoding on a codeword and a soft decision decoding on an error message block. The hard decision decoding on a codeword and the codeword comprises message blocks encoded with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method. When the hard decision decoding fails, the error message block to which the hard decision decoding fails among a plurality of the message blocks is identified. Soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block is generated and the soft decision decoding on the error message block based on the soft decision information is performed.

Flash memory system and operating method thereof

An operation method of a flash memory system includes reading data stored in a memory device, wherein the data is encoded by units of message blocks each including a row constituent code and a column constituent code by using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BC-BCH) method; performing a hard decision decoding on the read data; determining, when the hard decision decoding fails, a reference voltage for a message block having an error among the message blocks of the read data; and performing a soft decision decoding by using the determined reference voltage.

Operating method of flash memory system

An operation method of a flash memory system includes: obtaining first syndrome values to a codeword; obtaining locations of errors and the number of the locations of errors based on the first syndrome values; error-correcting the codeword by flipping bit values of error bits of the codeword based on the locations of errors to generate an error-corrected codeword; obtaining second syndrome values to the error-corrected codeword; determining whether an error is found in the error-corrected codeword based on the second syndrome values; changing the first syndrome values when it is determined that no error is found in the error-corrected codeword; and restoring the error-corrected codeword to the codeword by re-flipping the flipped bit values when it is determined that an error is found in the error-corrected codeword.

A method for arranging a plurality of message blocks in a lattice form and generating a message matrix includes deciding lengths of rows of the message matrix such that a length difference is equal to or less than a first critical point, deciding lengths of the message blocks such that a length difference is equal to or less than a second critical point, and arranging the message blocks in each row of the message matrix such that a length difference of columns of the message matrix is equal to or less than a third critical point.

Encoding device and method for generating message matrix

A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream.

Growing community of inventors

Daejeon, South Korea

Jeong-Seok Ha