Samsung Electronics Co., Ltd.

Jeong-Seok Chae

Hyo-Jin Kim

Yoon-Jay Cho

An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.

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Goynag-si, South Korea

Jeong-Seok Chae