Samsung Electronics Co., Ltd.

Jeong-lim Nam

Gi-Sung Yeo

Cha-Won Koh

Sang-Gyun Woo

Han-Ku Cho

Ji-young Lee

Byung-Hong Chung

Joon-Soo Park

Hyun Kyu Park

Seok-hwan Oh

Yool Kang

Jai-Hyuk Song

Cha-won Koh

Sang-Jin Kim

Kyeong-Koo Chi

Young-Hoo Kim

Seung-Pil Chung

Sung-Gon Jung

Dae-youp Lee

Won-Jin Kim

Guk-Hyon Yon

Heung-Sik Park

Jeung-woo Lee

Chang-Seob Kim

Do-yul Yoo

A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same

In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.

Method of manufacturing a semiconductor device

A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.

Method of forming fine metal patterns for a semiconductor device using a damascene process

Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

Nonvolatile memory device and method of manufacturing the same

A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.

Charge trapping type semiconductor memory device and method of manufacturing the same

Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.

Methods of fabricating a semiconductor device

A photoresist composition may include formulas 1 and 2: A method for forming photoresist patterns may include forming a photoresist layer on a semiconductor substrate and exposing and developing the photoresist layer using a mask pattern that includes first areas having a light transmissivity of about 100% and second areas having a light transmissivity of between about 10% and about 30%.

Photoresist composition and method of forming a photoresist pattern with a controlled remnant ratio

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